^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) ST-Ericsson SA 2010-2013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Rickard Andersson <rickard.andersson@stericsson.com> for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * ST-Ericsson.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Ulf Hansson <ulf.hansson@linaro.org> for Linaro.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irqchip/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_data/arm-ux500-pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "db8500-regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* ARM WFI Standby signal register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PRCM_ARM_WFI_STANDBY_WFI0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PRCM_ARM_WFI_STANDBY_WFI1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PRCM_IOCR (prcmu_base + 0x310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PRCM_IOCR_IOFORCE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Dual A9 core interrupt management unit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PRCM_A9_MASK_REQ (prcmu_base + 0x328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PRCM_A9_MASK_ACK (prcmu_base + 0x32c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PRCM_ARMITMSK95TO64 (prcmu_base + 0x124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PRCM_ARMITMSK127TO96 (prcmu_base + 0x128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PRCM_POWER_STATE_VAL (prcmu_base + 0x25C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PRCM_ARMITVAL31TO0 (prcmu_base + 0x260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PRCM_ARMITVAL63TO32 (prcmu_base + 0x264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PRCM_ARMITVAL95TO64 (prcmu_base + 0x268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void __iomem *prcmu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void __iomem *dist_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* This function decouple the gic from the prcmu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int prcmu_gic_decouple(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 val = readl(PRCM_A9_MASK_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Set bit 0 register value to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PRCM_A9_MASK_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Make sure the register is updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) readl(PRCM_A9_MASK_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Wait a few cycles for the gic mask completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* This function recouple the gic with the prcmu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int prcmu_gic_recouple(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 val = readl(PRCM_A9_MASK_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Set bit 0 register value to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PRCMU_GIC_NUMBER_REGS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * This function checks if there are pending irq on the gic. It only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * makes sense if the gic has been decoupled before with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * db8500_prcmu_gic_decouple function. Disabling an interrupt only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * disables the forwarding of the interrupt to any CPU interface. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * does not prevent the interrupt from changing state, for example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * becoming pending, or active and pending if it is already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * active. Hence, we have to check the interrupt is pending *and* is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) bool prcmu_gic_pending_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 pr; /* Pending register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 er; /* Enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* 5 registers. STI & PPI not skipped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (pr & er)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return true; /* There is a pending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * This function checks if there are pending interrupt on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * prcmu which has been delegated to monitor the irqs with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * db8500_prcmu_copy_gic_settings function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bool prcmu_pending_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 it, im;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) it = readl(PRCM_ARMITVAL31TO0 + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) im = readl(PRCM_ARMITMSK31TO0 + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (it & im)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return true; /* There is a pending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * This function checks if the specified cpu is in in WFI. It's usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * function. Of course passing smp_processor_id() to this function will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * always return false...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bool prcmu_is_cpu_in_wfi(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return readl(PRCM_ARM_WFI_STANDBY) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) (cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : PRCM_ARM_WFI_STANDBY_WFI0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * This function copies the gic SPI settings to the prcmu in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * monitor them and abort/finish the retention/off sequence or state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int prcmu_copy_gic_settings(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 er; /* Enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* We skip the STI and PPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) er = readl_relaxed(dist_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) GIC_DIST_ENABLE_SET + (i + 1) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) writel(er, PRCM_ARMITMSK31TO0 + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #ifdef CONFIG_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int ux500_suspend_enter(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int ux500_suspend_valid(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct platform_suspend_ops ux500_suspend_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .enter = ux500_suspend_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .valid = ux500_suspend_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define UX500_SUSPEND_OPS (&ux500_suspend_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define UX500_SUSPEND_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) void __init ux500_pm_init(u32 phy_base, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) prcmu_base = ioremap(phy_base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (!prcmu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pr_err("could not remap PRCMU for PM functions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dist_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (!dist_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pr_err("could not remap GIC dist base for PM functions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * On watchdog reboot the GIC is in some cases decoupled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * This will make sure that the GIC is correctly configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) prcmu_gic_recouple();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Set up ux500 suspend callbacks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) suspend_set_ops(UX500_SUSPEND_OPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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