Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) ST-Ericsson SA 2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef __MACH_DB8500_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define __MACH_DB8500_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) /* Base address and bank offsets for ESRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define U8500_ESRAM_BASE	0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define U8500_ESRAM_BANK_SIZE	0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define U8500_ESRAM_BANK0	U8500_ESRAM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define U8500_ESRAM_BANK1	(U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define U8500_ESRAM_BANK2	(U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define U8500_ESRAM_BANK3	(U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define U8500_ESRAM_BANK4	(U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * on V1 DMA uses 4KB for logical parameters position is right after the 64KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * reserved for security
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define U8500_ESRAM_DMA_LCPA_OFFSET     0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define U8500_DMA_LCPA_BASE    (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* This address fulfills the 256k alignment requirement of the lcla base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define U8500_DMA_LCLA_BASE	U8500_ESRAM_BANK4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define U8500_PER3_BASE		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define U8500_STM_BASE		0x80100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define U8500_STM_REG_BASE	(U8500_STM_BASE + 0xF000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define U8500_PER2_BASE		0x80110000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define U8500_PER1_BASE		0x80120000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define U8500_B2R2_BASE		0x80130000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define U8500_HSEM_BASE		0x80140000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define U8500_PER4_BASE		0x80150000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define U8500_TPIU_BASE		0x80190000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define U8500_ICN_BASE		0x81000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define U8500_BOOT_ROM_BASE	0x90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* ASIC ID is at 0xbf4 offset within this region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define U8500_ASIC_ID_BASE	0x9001D000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define U8500_PER6_BASE		0xa03c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define U8500_PER7_BASE		0xa03d0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define U8500_PER5_BASE		0xa03e0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define U8500_SVA_BASE		0xa0100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define U8500_SIA_BASE		0xa0200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define U8500_SGA_BASE		0xa0300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define U8500_MCDE_BASE		0xa0350000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define U8500_DMA_BASE		0x801C0000	/* v1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define U8500_SBAG_BASE		0xa0390000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define U8500_SCU_BASE		0xa0410000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define U8500_GIC_CPU_BASE	0xa0410100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define U8500_TWD_BASE		0xa0410600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define U8500_GIC_DIST_BASE	0xa0411000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define U8500_L2CC_BASE		0xa0412000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define U8500_MODEM_I2C		0xb7e02000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define U8500_GPIO0_BASE	(U8500_PER1_BASE + 0xE000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define U8500_GPIO1_BASE	(U8500_PER3_BASE + 0xE000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define U8500_GPIO2_BASE	(U8500_PER2_BASE + 0xE000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define U8500_GPIO3_BASE	(U8500_PER5_BASE + 0x1E000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define U8500_UART0_BASE	(U8500_PER1_BASE + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define U8500_UART1_BASE	(U8500_PER1_BASE + 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* per6 base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define U8500_RNG_BASE		(U8500_PER6_BASE + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define U8500_HASH0_BASE        (U8500_PER6_BASE + 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define U8500_HASH1_BASE        (U8500_PER6_BASE + 0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define U8500_PKA_BASE		(U8500_PER6_BASE + 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define U8500_PKAM_BASE		(U8500_PER6_BASE + 0x5100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define U8500_MTU0_BASE		(U8500_PER6_BASE + 0x6000) /* v1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define U8500_MTU1_BASE		(U8500_PER6_BASE + 0x7000) /* v1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define U8500_CR_BASE		(U8500_PER6_BASE + 0x8000) /* v1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define U8500_CRYP0_BASE	(U8500_PER6_BASE + 0xa000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define U8500_CRYP1_BASE	(U8500_PER6_BASE + 0xb000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define U8500_CLKRST6_BASE	(U8500_PER6_BASE + 0xf000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* per5 base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define U8500_USBOTG_BASE	(U8500_PER5_BASE + 0x00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define U8500_CLKRST5_BASE	(U8500_PER5_BASE + 0x1f000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* per4 base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define U8500_BACKUPRAM0_BASE	(U8500_PER4_BASE + 0x00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define U8500_BACKUPRAM1_BASE	(U8500_PER4_BASE + 0x01000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define U8500_RTT0_BASE		(U8500_PER4_BASE + 0x02000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define U8500_RTT1_BASE		(U8500_PER4_BASE + 0x03000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define U8500_RTC_BASE		(U8500_PER4_BASE + 0x04000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define U8500_SCR_BASE		(U8500_PER4_BASE + 0x05000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define U8500_DMC_BASE		(U8500_PER4_BASE + 0x06000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define U8500_PRCMU_BASE	(U8500_PER4_BASE + 0x07000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define U9540_DMC1_BASE		(U8500_PER4_BASE + 0x0A000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define U8500_PRCMU_TCDM_BASE	(U8500_PER4_BASE + 0x68000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define U8500_PRCMU_TCPM_BASE   (U8500_PER4_BASE + 0x60000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* per3 base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define U8500_FSMC_BASE		(U8500_PER3_BASE + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define U8500_SSP0_BASE		(U8500_PER3_BASE + 0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define U8500_SSP1_BASE		(U8500_PER3_BASE + 0x3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define U8500_I2C0_BASE		(U8500_PER3_BASE + 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define U8500_SDI2_BASE		(U8500_PER3_BASE + 0x5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define U8500_SKE_BASE		(U8500_PER3_BASE + 0x6000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define U8500_UART2_BASE	(U8500_PER3_BASE + 0x7000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define U8500_SDI5_BASE		(U8500_PER3_BASE + 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define U8500_CLKRST3_BASE	(U8500_PER3_BASE + 0xf000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* per2 base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define U8500_I2C3_BASE		(U8500_PER2_BASE + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define U8500_SPI2_BASE		(U8500_PER2_BASE + 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define U8500_SPI1_BASE		(U8500_PER2_BASE + 0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define U8500_PWL_BASE		(U8500_PER2_BASE + 0x3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define U8500_SDI4_BASE		(U8500_PER2_BASE + 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define U8500_MSP2_BASE		(U8500_PER2_BASE + 0x7000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define U8500_SDI1_BASE		(U8500_PER2_BASE + 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define U8500_SDI3_BASE		(U8500_PER2_BASE + 0x9000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define U8500_SPI0_BASE		(U8500_PER2_BASE + 0xa000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define U8500_HSIR_BASE		(U8500_PER2_BASE + 0xb000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define U8500_HSIT_BASE		(U8500_PER2_BASE + 0xc000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define U8500_CLKRST2_BASE	(U8500_PER2_BASE + 0xf000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* per1 base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define U8500_I2C1_BASE		(U8500_PER1_BASE + 0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define U8500_MSP0_BASE		(U8500_PER1_BASE + 0x3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define U8500_MSP1_BASE		(U8500_PER1_BASE + 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define U8500_MSP3_BASE		(U8500_PER1_BASE + 0x5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define U8500_SDI0_BASE		(U8500_PER1_BASE + 0x6000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define U8500_I2C2_BASE		(U8500_PER1_BASE + 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define U8500_SPI3_BASE		(U8500_PER1_BASE + 0x9000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define U8500_I2C4_BASE		(U8500_PER1_BASE + 0xa000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define U8500_SLIM0_BASE	(U8500_PER1_BASE + 0xb000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define U8500_CLKRST1_BASE	(U8500_PER1_BASE + 0xf000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define U8500_SHRM_GOP_INTERRUPT_BASE	0xB7C00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define U8500_GPIOBANK0_BASE	U8500_GPIO0_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define U8500_GPIOBANK1_BASE	(U8500_GPIO0_BASE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define U8500_GPIOBANK2_BASE	U8500_GPIO1_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define U8500_GPIOBANK3_BASE	(U8500_GPIO1_BASE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define U8500_GPIOBANK4_BASE	(U8500_GPIO1_BASE + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define U8500_GPIOBANK5_BASE	(U8500_GPIO1_BASE + 0x180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define U8500_GPIOBANK6_BASE	U8500_GPIO2_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define U8500_GPIOBANK7_BASE	(U8500_GPIO2_BASE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define U8500_GPIOBANK8_BASE	U8500_GPIO3_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define U8500_MCDE_SIZE		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define U8500_DSI_LINK_SIZE	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define U8500_DSI_LINK1_BASE	(U8500_MCDE_BASE + U8500_MCDE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define U8500_DSI_LINK2_BASE	(U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define U8500_DSI_LINK3_BASE	(U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define U8500_DSI_LINK_COUNT	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Modem and APE physical addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define U8500_MODEM_BASE	0xe000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define U8500_APE_BASE		0x6000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* SoC identification number information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define U8500_BB_UID_BASE      (U8500_BACKUPRAM1_BASE + 0xFC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Offsets to specific addresses in some IP blocks for DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MSP_TX_RX_REG_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CRYP1_RX_REG_OFFSET	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CRYP1_TX_REG_OFFSET	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HASH1_TX_REG_OFFSET	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  * Macros to get at IO space when running virtually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  * We dont map all the peripherals, let ioremap do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  * this for us. We map only very basic peripherals here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define U8500_IO_VIRTUAL	0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define U8500_IO_PHYSICAL	0xa0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* This is where we map in the ROM to check ASIC IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define UX500_VIRT_ROM		IOMEM(0xf0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* This macro is used in assembly, so no cast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IO_ADDRESS(x)           \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* typesafe io address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define __io_address(n)		IOMEM(IO_ADDRESS(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Used by some plat-nomadik code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define io_p2v(n)		__io_address(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ARRAY_AND_SIZE(x)	(x), ARRAY_SIZE(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #endif