^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NVIDIA Tegra SoC device tree board support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011, 2013, NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 Secret Lab Technologies, Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2010 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk/tegra.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pda_power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/usb/tegra_usb_phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/firmware/trusted_foundations.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <soc/tegra/pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/psci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "board.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "sleep.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Storage for debug-macro.S's state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * This must be in .data not .bss so that it gets initialized each time the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * kernel is loaded. The data is declared here rather than debug-macro.S so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * that multiple inclusions of debug-macro.S point at the same data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 tegra_uart_config[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Debug UART initialization required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Debug UART physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Debug UART virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void __init tegra_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) of_register_trusted_foundations();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) tegra_cpu_reset_handler_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) call_firmware_op(l2x0_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void __init tegra_dt_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) tegra_init_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) irqchip_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void __init tegra_dt_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct device *parent = tegra_soc_device_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) of_platform_default_populate(NULL, NULL, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void __init tegra_dt_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) tegra_init_suspend();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) of_machine_is_compatible("compal,paz00"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) tegra_paz00_wifikill_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) of_machine_is_compatible("nvidia,tegra20"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) platform_device_register_simple("tegra-cpuidle", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) of_machine_is_compatible("nvidia,tegra30"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const char * const tegra_dt_board_compat[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "nvidia,tegra124",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "nvidia,tegra114",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "nvidia,tegra30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "nvidia,tegra20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .l2c_aux_val = 0x3c400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .l2c_aux_mask = 0xc20fc3ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .smp = smp_ops(tegra_smp_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .map_io = tegra_map_common_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .init_early = tegra_init_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .init_irq = tegra_dt_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .init_machine = tegra_dt_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .init_late = tegra_dt_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .dt_compat = tegra_dt_board_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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