^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __MACH_TEGRA_SLEEP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __MACH_TEGRA_SLEEP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "irammap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) + IO_CPU_VIRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) + IO_PPSB_VIRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) + IO_PPSB_VIRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) + IO_APB_VIRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA_IRAM_RESET_BASE_VIRT (IO_IRAM_VIRT + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) TEGRA_IRAM_RESET_HANDLER_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PMC_SCRATCH37 0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PMC_SCRATCH38 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PMC_SCRATCH39 0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PMC_SCRATCH41 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifdef CONFIG_ARCH_TEGRA_2x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CPU_RESETTABLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CPU_RESETTABLE_SOON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CPU_NOT_RESETTABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA_FLUSH_CACHE_LOUIS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA_FLUSH_CACHE_ALL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #ifdef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* waits until the microsecond counter (base) is > rn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .macro wait_until, rn, base, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) add \rn, \rn, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 1001: ldr \tmp, [\base]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) cmp \tmp, \rn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) bmi 1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* returns the offset of the flow controller halt register for a cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .macro cpu_to_halt_reg rd, rcpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) cmp \rcpu, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) subne \rd, \rcpu, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) movne \rd, \rd, lsl #3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) addne \rd, \rd, #0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) moveq \rd, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* returns the offset of the flow controller csr register for a cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .macro cpu_to_csr_reg rd, rcpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) cmp \rcpu, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) subne \rd, \rcpu, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) movne \rd, \rd, lsl #3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) addne \rd, \rd, #0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) moveq \rd, #8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* returns the ID of the current processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .macro cpu_id, rd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mrc p15, 0, \rd, c0, c0, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) and \rd, \rd, #0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* loads a 32-bit value into a register without a data access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .macro mov32, reg, val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) movw \reg, #:lower16:\val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) movt \reg, #:upper16:\val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Marco to check CPU part num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .macro check_cpu_part_num part_num, tmp1, tmp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mrc p15, 0, \tmp1, c0, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ubfx \tmp1, \tmp1, #4, #12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mov32 \tmp2, \part_num
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) cmp \tmp1, \tmp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Macro to exit SMP coherency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .macro exit_smp, tmp1, tmp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #ifdef CONFIG_HAVE_ARM_SCU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) check_cpu_part_num 0xc09, \tmp1, \tmp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mrceq p15, 0, \tmp1, c0, c0, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) andeq \tmp1, \tmp1, #0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) moveq \tmp1, \tmp1, lsl #2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) moveq \tmp2, #0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) moveq \tmp2, \tmp2, lsl \tmp1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ldreq \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) streq \tmp2, [\tmp1] @ invalidate SCU tags for CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Macro to check Tegra revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define APB_MISC_GP_HIDREV 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .macro tegra_get_soc_id base, tmp1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mov32 \tmp1, \base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ldr \tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) and \tmp1, \tmp1, #0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) mov \tmp1, \tmp1, lsr #8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void tegra_resume(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int tegra_sleep_cpu_finish(unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void tegra_disable_clean_inv_dcache(u32 flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) void tegra20_hotplug_shutdown(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void tegra30_hotplug_shutdown(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void tegra20_tear_down_cpu(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void tegra30_tear_down_cpu(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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