Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <soc/tegra/flowctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "sleep.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PMC_SCRATCH41	0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *	tegra_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *	  CPU boot vector when restarting the a CPU following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *	  an LP2 transition. Also branched to by LP0 and LP1 resume after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *	  re-enabling sdram.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *	r6: SoC ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *	r8: CPU part number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) ENTRY(tegra_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	check_cpu_part_num 0xc09, r8, r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	bleq	v7_invalidate_l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	cpu_id	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	cmp	r0, #0				@ CPU0?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  THUMB(	it	ne )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	bne	cpu_resume			@ no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	/* Are we on Tegra20? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	cmp	r6, #TEGRA20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	beq	1f				@ Yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/* Clear the flow controller flags for this CPU. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	cpu_to_csr_reg r3, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	mov32	r2, TEGRA_FLOW_CTRL_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	ldr	r1, [r2, r3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/* Clear event & intr flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	orr	r1, r1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		#FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	movw	r0, #0x3FFD	@ enable, cluster_switch, immed, bitmaps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 				@ & ext flags for CPU power mgnt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	bic	r1, r1, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	str	r1, [r2, r3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	mov32	r9, 0xc09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	cmp	r8, r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	bne	end_ca9_scu_l2_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #ifdef CONFIG_HAVE_ARM_SCU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* enable SCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	mov32	r0, TEGRA_ARM_PERIF_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	ldr	r1, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	orr	r1, r1, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	str	r1, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	bl	tegra_resume_trusted_foundations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	/* L2 cache resume & re-enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	bl	l2c310_early_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) end_ca9_scu_l2_resume:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	mov32	r9, 0xc0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	cmp	r8, r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	bleq	tegra_init_l2_for_a15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	b	cpu_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) ENDPROC(tegra_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  *	tegra_resume_trusted_foundations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  *	  Trusted Foundations firmware initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  *	Doesn't return if firmware presents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  *	Corrupted registers: r1, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) ENTRY(tegra_resume_trusted_foundations)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/* Check whether Trusted Foundations firmware presents. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	mov32	r2, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	ldr	r1, =__tegra_cpu_reset_handler_data_offset + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 							RESET_DATA(TF_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	ldr	r1, [r2, r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	cmp	r1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	reteq	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  .arch_extension sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 * First call after suspend wakes firmware. No arguments required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 * for some firmware versions. Downstream kernel of ASUS TF300T uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 * r0=3 for the wake-up notification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	mov	r0, #3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	smc	#0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	b	cpu_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ENDPROC(tegra_resume_trusted_foundations)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.align L1_CACHE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ENTRY(__tegra_cpu_reset_handler_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  * __tegra_cpu_reset_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  * Common handler for all CPU reset events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * Register usage within the reset handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  *      Others: scratch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  *      R6  = SoC ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  *      R7  = CPU present (to the OS) mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  *      R8  = CPU in LP1 state mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  *      R9  = CPU in LP2 state mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  *      R10 = CPU number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  *      R11 = CPU mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  *      R12 = pointer to reset handler data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * NOTE: This code is copied to IRAM. All code and data accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  *       must be position-independent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.arm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.align L1_CACHE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ENTRY(__tegra_cpu_reset_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	cpsid	aif, 0x13			@ SVC mode, interrupts disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	adr	r12, __tegra_cpu_reset_handler_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ldr	r5, [r12, #RESET_DATA(TF_PRESENT)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	cmp	r5, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	bne	after_errata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #ifdef CONFIG_ARCH_TEGRA_2x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) t20_check:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	cmp	r6, #TEGRA20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	bne	after_t20_check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) t20_errata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	# Tegra20 is a Cortex-A9 r1p1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	mrc	p15, 0, r0, c1, c0, 0   @ read system control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	orr	r0, r0, #1 << 14        @ erratum 716044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	mcr	p15, 0, r0, c1, c0, 0   @ write system control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	mrc	p15, 0, r0, c15, c0, 1  @ read diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	orr	r0, r0, #1 << 4         @ erratum 742230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	orr	r0, r0, #1 << 11        @ erratum 751472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	mcr	p15, 0, r0, c15, c0, 1  @ write diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	b	after_errata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) after_t20_check:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #ifdef CONFIG_ARCH_TEGRA_3x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) t30_check:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	cmp	r6, #TEGRA30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	bne	after_t30_check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) t30_errata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	# Tegra30 is a Cortex-A9 r2p9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	mrc	p15, 0, r0, c15, c0, 1  @ read diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	orr	r0, r0, #1 << 6         @ erratum 743622
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	orr	r0, r0, #1 << 11        @ erratum 751472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	mcr	p15, 0, r0, c15, c0, 1  @ write diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	b	after_errata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) after_t30_check:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) after_errata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	mrc	p15, 0, r10, c0, c0, 5		@ MPIDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	and	r10, r10, #0x3			@ R10 = CPU number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	mov	r11, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	mov	r11, r11, lsl r10  		@ R11 = CPU mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* Does the OS know about this CPU? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	ldr	r7, [r12, #RESET_DATA(MASK_PRESENT)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	tst	r7, r11 			@ if !present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	bleq	__die				@ CPU not present (to OS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* Waking up from LP1? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	ldr	r8, [r12, #RESET_DATA(MASK_LP1)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	tst	r8, r11				@ if in_lp1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	beq	__is_not_lp1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	cmp	r10, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	bne	__die				@ only CPU0 can be here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ldr	lr, [r12, #RESET_DATA(STARTUP_LP1)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	cmp	lr, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	bleq	__die				@ no LP1 startup handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  THUMB(	add	lr, lr, #1 )			@ switch to Thumb mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	bx	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) __is_not_lp1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	/* Waking up from LP2? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	ldr	r9, [r12, #RESET_DATA(MASK_LP2)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	tst	r9, r11				@ if in_lp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	beq	__is_not_lp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	ldr	lr, [r12, #RESET_DATA(STARTUP_LP2)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	cmp	lr, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	bleq	__die				@ no LP2 startup handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	bx	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) __is_not_lp2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 * Can only be secondary boot (initial or hotplug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 * CPU0 can't be here for Tegra20/30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	cmp	r6, #TEGRA114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	beq	__no_cpu0_chk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	cmp	r10, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	bleq	__die				@ CPU0 cannot be here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) __no_cpu0_chk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	ldr	lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	cmp	lr, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	bleq	__die				@ no secondary startup handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	bx	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  * We don't know why the CPU reset. Just kill it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  * The LR register will contain the address we died at + 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) __die:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	sub	lr, lr, #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	mov32	r7, TEGRA_PMC_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	str	lr, [r7, #PMC_SCRATCH41]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	mov32	r7, TEGRA_CLK_RESET_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/* Are we on Tegra20? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	cmp	r6, #TEGRA20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	bne	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #ifdef CONFIG_ARCH_TEGRA_2x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	mov32	r0, 0x1111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	mov	r1, r0, lsl r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	str	r1, [r7, #0x340]		@ CLK_RST_CPU_CMPLX_SET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #ifdef CONFIG_ARCH_TEGRA_3x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	mov32	r6, TEGRA_FLOW_CTRL_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	cmp	r10, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	moveq	r1, #FLOW_CTRL_HALT_CPU0_EVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	moveq	r2, #FLOW_CTRL_CPU0_CSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	movne	r1, r10, lsl #3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	addne	r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	addne	r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/* Clear CPU "event" and "interrupt" flags and power gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	   it when halting but not before it is in the "WFI" state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	ldr	r0, [r6, +r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	orr	r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	orr	r0, r0, #FLOW_CTRL_CSR_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	str	r0, [r6, +r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	/* Unconditionally halt this CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	mov	r0, #FLOW_CTRL_WAITEVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	str	r0, [r6, +r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	ldr	r0, [r6, +r1]			@ memory barrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	wfi					@ CPU should be power gated here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/* If the CPU didn't power gate above just kill it's clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	mov	r0, r11, lsl #8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	str	r0, [r7, #348]			@ CLK_CPU_CMPLX_SET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	/* If the CPU still isn't dead, just spin here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	b	.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ENDPROC(__tegra_cpu_reset_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.align L1_CACHE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.type	__tegra_cpu_reset_handler_data, %object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.globl	__tegra_cpu_reset_handler_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.globl	__tegra_cpu_reset_handler_data_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.equ	__tegra_cpu_reset_handler_data_offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 					. - __tegra_cpu_reset_handler_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) __tegra_cpu_reset_handler_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	.rept   TEGRA_RESET_DATA_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.long   0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.endr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.align L1_CACHE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ENTRY(__tegra_cpu_reset_handler_end)