Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2011 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *	Colin Cross <ccross@android.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 2010,2013, NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqchip/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <soc/tegra/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "board.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SGI_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void __iomem *tegra_gic_cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) bool tegra_pending_sgi(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	u32 pending_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	pending_set = readl_relaxed(distbase + GIC_DIST_PENDING_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	if (pending_set & SGI_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int tegra_gic_notifier(struct notifier_block *self,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			      unsigned long cmd, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	case CPU_PM_ENTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct notifier_block tegra_gic_notifier_block = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	.notifier_call = tegra_gic_notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const struct of_device_id tegra114_dt_gic_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	{ .compatible = "arm,cortex-a15-gic" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void __init tegra114_gic_cpu_pm_registration(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	struct device_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	dn = of_find_matching_node(NULL, tegra114_dt_gic_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	if (!dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	tegra_gic_cpu_base = of_iomap(dn, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	cpu_pm_register_notifier(&tegra_gic_notifier_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void __init tegra114_gic_cpu_pm_registration(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct of_device_id tegra_ictlr_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	{ .compatible = "nvidia,tegra20-ictlr" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	{ .compatible = "nvidia,tegra30-ictlr" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void __init tegra_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 	if (WARN_ON(!of_find_matching_node(NULL, tegra_ictlr_match)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 		pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 	tegra114_gic_cpu_pm_registration();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }