^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Colin Cross <ccross@google.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Erik Gilling <konkers@google.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __MACH_TEGRA_IOMAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __MACH_TEGRA_IOMAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA_IRAM_BASE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEGRA_IRAM_SIZE SZ_256K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA_ARM_PERIF_BASE 0x50040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA_ARM_PERIF_SIZE SZ_8K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA_ARM_INT_DIST_BASE 0x50041000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA_ARM_INT_DIST_SIZE SZ_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA_TMR1_BASE 0x60005000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA_TMR1_SIZE SZ_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA_TMR2_BASE 0x60005008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA_TMR2_SIZE SZ_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA_TMRUS_BASE 0x60005010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA_TMRUS_SIZE SZ_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA_TMR3_BASE 0x60005050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA_TMR3_SIZE SZ_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA_TMR4_BASE 0x60005058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA_TMR4_SIZE SZ_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA_CLK_RESET_BASE 0x60006000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA_CLK_RESET_SIZE SZ_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA_FLOW_CTRL_BASE 0x60007000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA_FLOW_CTRL_SIZE 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA_SB_BASE 0x6000C200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA_SB_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA_APB_MISC_BASE 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA_APB_MISC_SIZE SZ_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA_UARTA_BASE 0x70006000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TEGRA_UARTA_SIZE SZ_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TEGRA_UARTB_BASE 0x70006040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TEGRA_UARTB_SIZE SZ_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TEGRA_UARTC_BASE 0x70006200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEGRA_UARTC_SIZE SZ_256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA_UARTD_BASE 0x70006300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEGRA_UARTD_SIZE SZ_256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA_UARTE_BASE 0x70006400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TEGRA_UARTE_SIZE SZ_256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEGRA_PMC_BASE 0x7000E400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TEGRA_PMC_SIZE SZ_256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TEGRA_EMC_BASE 0x7000F400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TEGRA_EMC_SIZE SZ_1K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TEGRA_EMC0_BASE 0x7001A000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TEGRA_EMC0_SIZE SZ_2K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TEGRA_EMC1_BASE 0x7001A800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TEGRA_EMC1_SIZE SZ_2K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TEGRA124_EMC_BASE 0x7001B000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TEGRA124_EMC_SIZE SZ_2K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TEGRA_CSITE_BASE 0x70040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TEGRA_CSITE_SIZE SZ_256K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* On TEGRA, many peripherals are very closely packed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * two 256MB io windows (that actually only use about 64KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * at the start of each).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * We will just map the first MMU section of each window (to minimize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * pt entries needed) and provide a macro to transform physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * io addresses to an appropriate void __iomem *.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IO_IRAM_PHYS 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IO_IRAM_VIRT IOMEM(0xFE400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IO_IRAM_SIZE SZ_256K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IO_CPU_PHYS 0x50040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IO_CPU_VIRT IOMEM(0xFE440000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IO_CPU_SIZE SZ_16K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IO_PPSB_PHYS 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IO_PPSB_VIRT IOMEM(0xFE200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IO_PPSB_SIZE SECTION_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IO_APB_PHYS 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IO_APB_VIRT IOMEM(0xFE000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IO_APB_SIZE SECTION_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IO_TO_VIRT(n) ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IO_ADDRESS(n) (IO_TO_VIRT(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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