^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * SMP support for Allwinner SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2012-2013 Allwinner Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CPUCFG_CPU_STATUS_REG(cpu) (((cpu) + 1) * 0x40 + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CPUCFG_GEN_CTRL_REG 0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CPUCFG_PRIVATE0_REG 0x1a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CPUCFG_PRIVATE1_REG 0x1a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CPUCFG_DBG_CTL0_REG 0x1e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CPUCFG_DBG_CTL1_REG 0x1e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PRCM_CPU_PWROFF_REG 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PRCM_CPU_PWR_CLAMP_REG(cpu) (((cpu) * 4) + 0x140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void __iomem *cpucfg_membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void __iomem *prcm_membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static DEFINE_SPINLOCK(cpu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pr_err("Missing A31 PRCM node in the device tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) prcm_membase = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (!prcm_membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) pr_err("Couldn't map A31 PRCM registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) node = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "allwinner,sun6i-a31-cpuconfig");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pr_err("Missing A31 CPU config node in the device tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) cpucfg_membase = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (!cpucfg_membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pr_err("Couldn't map A31 CPU config registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int sun6i_smp_boot_secondary(unsigned int cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (!(prcm_membase && cpucfg_membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) spin_lock(&cpu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Set CPU boot address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) writel(__pa_symbol(secondary_startup),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) cpucfg_membase + CPUCFG_PRIVATE0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Assert the CPU core in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Assert the L1 cache in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Disable external debug access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Power up the CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) for (i = 0; i <= 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Clear CPU power-off gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Deassert the CPU core reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Enable back the external debug accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) spin_unlock(&cpu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct smp_operations sun6i_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .smp_prepare_cpus = sun6i_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .smp_boot_secondary = sun6i_smp_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) CPU_METHOD_OF_DECLARE(sun6i_a31_smp, "allwinner,sun6i-a31", &sun6i_smp_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void __init sun8i_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) node = of_find_compatible_node(NULL, NULL, "allwinner,sun8i-a23-prcm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pr_err("Missing A23 PRCM node in the device tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) prcm_membase = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!prcm_membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pr_err("Couldn't map A23 PRCM registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) node = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "allwinner,sun8i-a23-cpuconfig");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pr_err("Missing A23 CPU config node in the device tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) cpucfg_membase = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!cpucfg_membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pr_err("Couldn't map A23 CPU config registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int sun8i_smp_boot_secondary(unsigned int cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (!(prcm_membase && cpucfg_membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) spin_lock(&cpu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Set CPU boot address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writel(__pa_symbol(secondary_startup),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) cpucfg_membase + CPUCFG_PRIVATE0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Assert the CPU core in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Assert the L1 cache in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Clear CPU power-off gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Deassert the CPU core reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) spin_unlock(&cpu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct smp_operations sun8i_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .smp_prepare_cpus = sun8i_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .smp_boot_secondary = sun8i_smp_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CPU_METHOD_OF_DECLARE(sun8i_a23_smp, "allwinner,sun8i-a23", &sun8i_smp_ops);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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