Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2018 Chen-Yu Tsai
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (c) 2018 Bootlin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Chen-Yu Tsai <wens@csie.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Mylène Josserand <mylene.josserand@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * SMP support for sunxi based systems with Cortex A7/A15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ENTRY(sunxi_mc_smp_cluster_cache_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	.arch	armv7-a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	 * Enable cluster-level coherency, in preparation for turning on the MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	 * Also enable regional clock gating and L2 data latency settings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	 * Cortex-A15. These settings are from the vendor kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	mrc	p15, 0, r1, c0, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	movw	r2, #(ARM_CPU_PART_MASK & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	movt	r2, #(ARM_CPU_PART_MASK >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	and	r1, r1, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	movw	r2, #(ARM_CPU_PART_CORTEX_A15 & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	movt	r2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	cmp	r1, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	bne	not_a15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	/* The following is Cortex-A15 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	/* ACTLR2: Enable CPU regional clock gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	mrc p15, 1, r1, c15, c0, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	orr r1, r1, #(0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	mcr p15, 1, r1, c15, c0, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	/* L2ACTLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	mrc p15, 1, r1, c15, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	/* Enable L2, GIC, and Timer regional clock gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	orr r1, r1, #(0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	/* Disable clean/evict from being pushed to external */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	orr r1, r1, #(0x1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	mcr p15, 1, r1, c15, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	/* L2CTRL: L2 data RAM latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	mrc p15, 1, r1, c9, c0, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	bic r1, r1, #(0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	orr r1, r1, #(0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	mcr p15, 1, r1, c9, c0, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	/* End of Cortex-A15 specific setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	not_a15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	/* Get value of sunxi_mc_smp_first_comer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	adr	r1, first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	ldr	r0, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	ldr	r0, [r1, r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	/* Skip cci_enable_port_for_self if not first comer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	cmp	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	bxeq	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	b	cci_enable_port_for_self
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	.align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	first: .word sunxi_mc_smp_first_comer - .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ENDPROC(sunxi_mc_smp_cluster_cache_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ENTRY(sunxi_mc_smp_secondary_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	bl	sunxi_mc_smp_cluster_cache_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	bl	secure_cntvoff_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	b	secondary_startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ENDPROC(sunxi_mc_smp_secondary_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ENTRY(sunxi_mc_smp_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	bl	sunxi_mc_smp_cluster_cache_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	b	cpu_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ENDPROC(sunxi_mc_smp_resume)