^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-sti/platsmp.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * http://www.st.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2002 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/smp_scu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "smp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static u32 __iomem *cpu_strt_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned long entry_pa = __pa_symbol(secondary_startup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Secondary CPU is initialised and started by a U-BOOTROM firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Secondary CPU is spinning and waiting for a write at cpu_strt_ptr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Writing secondary_startup address at cpu_strt_ptr makes it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * jump directly to secondary_startup().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) __raw_writel(entry_pa, cpu_strt_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* wmb so that data is actually written before cache flush is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) sync_cache_w(cpu_strt_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void __iomem *scu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 release_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) scu_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) scu_enable(scu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (max_cpus <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) np = of_get_cpu_node(cpu, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (of_property_read_u32(np, "cpu-release-addr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) &release_phys)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pr_err("CPU %d: missing or invalid cpu-release-addr "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "property\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * cpu-release-addr is usually configured in SBC DMEM but can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * also be in RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!memblock_is_memory(release_phys))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) cpu_strt_ptr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ioremap(release_phys, sizeof(release_phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) cpu_strt_ptr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) (u32 __iomem *)phys_to_virt(release_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) set_cpu_possible(cpu, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) const struct smp_operations sti_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .smp_prepare_cpus = sti_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .smp_boot_secondary = sti_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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