^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/plat-spear/time.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2010 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Shiraz Hashim<shiraz.linux.kernel@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * We would use TIMER0 and TIMER1 as clockevent and clocksource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * they share same functional clock. Any change in one's functional clock will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * also affect other timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLKEVT 0 /* gpt0, channel0 as clockevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLKSRC 1 /* gpt0, channel1 as clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Register offsets, x is channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CR(x) ((x) * 0x80 + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IR(x) ((x) * 0x80 + 0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LOAD(x) ((x) * 0x80 + 0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define COUNT(x) ((x) * 0x80 + 0x8C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Reg bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CTRL_INT_ENABLE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CTRL_ENABLE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CTRL_ONE_SHOT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CTRL_PRESCALER1 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CTRL_PRESCALER2 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CTRL_PRESCALER4 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CTRL_PRESCALER8 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CTRL_PRESCALER16 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CTRL_PRESCALER32 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CTRL_PRESCALER64 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CTRL_PRESCALER128 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CTRL_PRESCALER256 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define INT_STATUS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Minimum clocksource/clockevent timer range in seconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPEAR_MIN_RANGE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static __iomem void *gpt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static struct clk *gpt_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int clockevent_next_event(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clock_event_device *clk_event_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void __init spear_clocksource_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 tick_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* program the prescaler (/256)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* find out actual clock driving Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tick_rate = clk_get_rate(gpt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) tick_rate >>= CTRL_PRESCALER256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) writew(0xFFFF, gpt_base + LOAD(CLKSRC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) val = readw(gpt_base + CR(CLKSRC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) val &= ~CTRL_ONE_SHOT; /* autoreload mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) val |= CTRL_ENABLE ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writew(val, gpt_base + CR(CLKSRC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* register the clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 200, 16, clocksource_mmio_readw_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static inline void timer_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u16 val = readw(gpt_base + CR(CLKEVT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* stop the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val &= ~CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) writew(val, gpt_base + CR(CLKEVT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int spear_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) timer_shutdown(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int spear_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* stop the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) timer_shutdown(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) val = readw(gpt_base + CR(CLKEVT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) val |= CTRL_ONE_SHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) writew(val, gpt_base + CR(CLKEVT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int spear_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* stop the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) timer_shutdown(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) period = clk_get_rate(gpt_clk) / HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) period >>= CTRL_PRESCALER16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writew(period, gpt_base + LOAD(CLKEVT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val = readw(gpt_base + CR(CLKEVT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) val &= ~CTRL_ONE_SHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) val |= CTRL_ENABLE | CTRL_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writew(val, gpt_base + CR(CLKEVT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct clock_event_device clkevt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .name = "tmr0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .set_state_shutdown = spear_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .set_state_periodic = spear_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .set_state_oneshot = spear_set_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .tick_resume = spear_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .set_next_event = clockevent_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .shift = 0, /* to be computed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int clockevent_next_event(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clock_event_device *clk_event_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u16 val = readw(gpt_base + CR(CLKEVT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (val & CTRL_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) writew(cycles, gpt_base + LOAD(CLKEVT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val |= CTRL_ENABLE | CTRL_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) writew(val, gpt_base + CR(CLKEVT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct clock_event_device *evt = &clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) writew(INT_STATUS, gpt_base + IR(CLKEVT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void __init spear_clockevent_init(int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 tick_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* program the prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) tick_rate = clk_get_rate(gpt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tick_rate >>= CTRL_PRESCALER16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) clkevt.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (request_irq(irq, spear_timer_interrupt, IRQF_TIMER, "timer", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pr_err("Failed to request irq %d (timer)\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct of_device_id timer_of_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { .compatible = "st,spear-timer", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void __init spear_setup_of_timer(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) np = of_find_matching_node(NULL, timer_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pr_err("%s: No timer passed via DT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pr_err("%s: No irq passed for timer via DT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) gpt_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!gpt_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pr_err("%s: of iomap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) gpt_clk = clk_get_sys("gpt0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (IS_ERR(gpt_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pr_err("%s:couldn't get clk for gpt\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto err_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = clk_prepare_enable(gpt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) goto err_prepare_enable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) spear_clockevent_init(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) spear_clocksource_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) err_prepare_enable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) clk_put(gpt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) err_iomap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) iounmap(gpt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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