Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * arch/arm/plat-spear/pl080.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * DMAC pl080 definitions for SPEAr platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/amba/pl08x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/amba/bus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spinlock_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <mach/spear.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <mach/misc_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	unsigned char busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) } signals[16] = {{0, 0}, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int pl080_get_signal(const struct pl08x_channel_data *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	unsigned int signal = cd->min_signal, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	spin_lock_irqsave(&lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	/* Return if signal is already acquired by somebody else */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	if (signals[signal].busy &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			(signals[signal].val != cd->muxval)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		spin_unlock_irqrestore(&lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	/* If acquiring for the first time, configure it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	if (!signals[signal].busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		val = readl(DMA_CHN_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		 * Each request line has two bits in DMA_CHN_CFG register. To
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		 * goto the bits of current request line, do left shift of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		 * value by 2 * signal number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		val &= ~(0x3 << (signal * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		val |= cd->muxval << (signal * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		writel(val, DMA_CHN_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	signals[signal].busy++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	signals[signal].val = cd->muxval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	spin_unlock_irqrestore(&lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	return signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void pl080_put_signal(const struct pl08x_channel_data *cd, int signal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	spin_lock_irqsave(&lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	/* if signal is not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	if (!signals[signal].busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	signals[signal].busy--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	spin_unlock_irqrestore(&lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }