^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012-2015 Altera Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/reset/socfpga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) void __iomem *sys_manager_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) void __iomem *rst_manager_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) void __iomem *sdr_ctl_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned long socfpga_cpu1start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static void __init socfpga_sysmgr_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (of_property_read_u32(np, "cpu1-start-addr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) (u32 *) &socfpga_cpu1start_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) pr_err("SMP: Need cpu1-start-addr in device tree.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) sync_cache_w(&socfpga_cpu1start_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) sys_manager_base_addr = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) rst_manager_base_addr = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) sdr_ctl_base_addr = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void __init socfpga_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) irqchip_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) socfpga_sysmgr_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) socfpga_init_l2_ecc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) socfpga_init_ocram_ecc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) socfpga_reset_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void __init socfpga_arria10_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) irqchip_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) socfpga_sysmgr_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) socfpga_init_arria10_l2_ecc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) socfpga_init_arria10_ocram_ecc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) socfpga_reset_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (mode == REBOOT_WARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) temp |= RSTMGR_CTRL_SWWARMRSTREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (mode == REBOOT_WARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) temp |= RSTMGR_CTRL_SWWARMRSTREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const char *altera_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "altr,socfpga",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .l2c_aux_val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .l2c_aux_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .init_irq = socfpga_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .restart = socfpga_cyclone5_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .dt_compat = altera_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const char *altera_a10_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "altr,socfpga-arria10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .l2c_aux_val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .l2c_aux_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .init_irq = socfpga_arria10_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .restart = socfpga_arria10_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .dt_compat = altera_a10_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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