^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014-2015 Altera Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define MAX_LOOP_COUNT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* Register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SDR_CTRLGRP_LOWPWREQ_ADDR 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SDR_CTRLGRP_LOWPWRACK_ADDR 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Bitfield positions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SELFRSHREQ_POS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SELFRSHREQ_MASK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SELFRFSHACK_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SELFRFSHACK_MASK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * This code assumes that when the bootloader configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * the sdram controller for the DDR on the board it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * configured the following fields depending on the DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * vendor/configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * sdr.ctrlcfg.lowpwreq.selfrfshmask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * sdr.ctrlcfg.lowpwrtiming.clkdisablecycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * sdr.ctrlcfg.dramtiming4.selfrfshexit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .arch armv7-a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .align 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * socfpga_sdram_self_refresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * r0 : sdr_ctl_base_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * r1 : temp storage of return value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * r2 : temp storage of register values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * r3 : loop counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * return value: lower 16 bits: loop count going into self refresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * upper 16 bits: loop count exiting self refresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ENTRY(socfpga_sdram_self_refresh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Enable dynamic clock gating in the Power Control Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mrc p15, 0, r2, c15, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) orr r2, r2, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mcr p15, 0, r2, c15, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ldr r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) orr r2, r2, #SELFRSHREQ_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) str r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Poll until sdr.ctrlgrp.lowpwrack.selfrfshack == 1 or hit max loops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mov r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) while_ack_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ldr r2, [r0, #SDR_CTRLGRP_LOWPWRACK_ADDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) and r2, r2, #SELFRFSHACK_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) cmp r2, #SELFRFSHACK_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) beq ack_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) add r3, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) cmp r3, #MAX_LOOP_COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bne while_ack_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ack_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mov r1, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Execute an ISB instruction to ensure that all of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * CP15 register changes have been committed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Execute a barrier instruction to ensure that all cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * TLB and branch predictor maintenance operations issued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * by any CPU in the cluster have completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dmb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) wfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ldr r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bic r2, r2, #SELFRSHREQ_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) str r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Poll until sdr.ctrlgrp.lowpwrack.selfrfshack == 0 or hit max loops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mov r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) while_ack_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ldr r2, [r0, #SDR_CTRLGRP_LOWPWRACK_ADDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) and r2, r2, #SELFRFSHACK_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) cmp r2, #SELFRFSHACK_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bne ack_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) add r3, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) cmp r3, #MAX_LOOP_COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) bne while_ack_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ack_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Prepare return value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Shift loop count for exiting self refresh into upper 16 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Leave loop count for requesting self refresh in lower 16 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mov r3, r3, lsl #16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) add r1, r1, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Disable dynamic clock gating in the Power Control Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mrc p15, 0, r2, c15, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bic r2, r2, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) mcr p15, 0, r2, c15, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mov r0, r1 @ return value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) bx lr @ return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ENDPROC(socfpga_sdram_self_refresh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ENTRY(socfpga_sdram_self_refresh_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .word . - socfpga_sdram_self_refresh
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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