^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2010-2011 Calxeda, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2012 Pavel Machek <pavel@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012 Altera Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/smp_scu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int trampoline_size = secondary_trampoline_end - secondary_trampoline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) if (socfpga_cpu1start_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* This will put CPU #1 into reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) writel(RSTMGR_MPUMODRST_CPU1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) memcpy(phys_to_virt(0), secondary_trampoline, trampoline_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) writel(__pa_symbol(secondary_startup),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) outer_clean_range(0, trampoline_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* This will release CPU #1 out of reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) writel(0, rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int trampoline_size = secondary_trampoline_end - secondary_trampoline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (socfpga_cpu1start_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SOCFPGA_A10_RSTMGR_MODMPURST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) memcpy(phys_to_virt(0), secondary_trampoline, trampoline_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) writel(__pa_symbol(secondary_startup),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) outer_clean_range(0, trampoline_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* This will release CPU #1 out of reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) writel(0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_MODMPURST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __iomem *socfpga_scu_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pr_err("%s: missing scu\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) socfpga_scu_base_addr = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (!socfpga_scu_base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) scu_enable(socfpga_scu_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * platform-specific code to shutdown a CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Called with IRQs disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void socfpga_cpu_die(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Do WFI. If we wake up early, go back into WFI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * We need a dummy function so that platform_can_cpu_hotplug() knows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * we support CPU hotplug. However, the function does not need to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * anything, because CPUs going offline just do WFI. We could reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * the CPUs but it would increase power consumption.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int socfpga_cpu_kill(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct smp_operations socfpga_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .smp_prepare_cpus = socfpga_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .smp_boot_secondary = socfpga_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .cpu_die = socfpga_cpu_die,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .cpu_kill = socfpga_cpu_kill,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct smp_operations socfpga_a10_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .smp_prepare_cpus = socfpga_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .smp_boot_secondary = socfpga_a10_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .cpu_die = socfpga_cpu_die,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .cpu_kill = socfpga_cpu_kill,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) CPU_METHOD_OF_DECLARE(socfpga_smp, "altr,socfpga-smp", &socfpga_smp_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) CPU_METHOD_OF_DECLARE(socfpga_a10_smp, "altr,socfpga-a10-smp", &socfpga_a10_smp_ops);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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