Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright Altera Corporation (C) 2016. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* A10 System Manager L2 ECC Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define A10_MPU_CTRL_L2_ECC_OFST          0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define A10_MPU_CTRL_L2_ECC_EN            BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* A10 System Manager Global IRQ Mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define A10_SYSMGR_ECC_INTMASK_CLR_OFST   0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define A10_SYSMGR_ECC_INTMASK_CLR_L2     BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* A10 System Manager L2 ECC IRQ Clear register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define A10_SYSMGR_MPU_CLEAR_L2_ECC_OFST  0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define A10_SYSMGR_MPU_CLEAR_L2_ECC       (BIT(31) | BIT(15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) void socfpga_init_l2_ecc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	void __iomem *mapped_l2_edac_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	np = of_find_compatible_node(NULL, NULL, "altr,socfpga-l2-ecc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		pr_err("Unable to find socfpga-l2-ecc in dtb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	mapped_l2_edac_addr = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	if (!mapped_l2_edac_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		pr_err("Unable to find L2 ECC mapping in dtb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	/* Enable ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	writel(0x01, mapped_l2_edac_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	iounmap(mapped_l2_edac_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void socfpga_init_arria10_l2_ecc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	void __iomem *mapped_l2_edac_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	/* Find the L2 EDAC device tree node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	np = of_find_compatible_node(NULL, NULL, "altr,socfpga-a10-l2-ecc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		pr_err("Unable to find socfpga-a10-l2-ecc in dtb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	mapped_l2_edac_addr = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	if (!mapped_l2_edac_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		pr_err("Unable to find L2 ECC mapping in dtb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	if (!sys_manager_base_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		pr_err("System Manager not mapped for L2 ECC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	/* Clear any pending IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	writel(A10_SYSMGR_MPU_CLEAR_L2_ECC, (sys_manager_base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	       A10_SYSMGR_MPU_CLEAR_L2_ECC_OFST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	/* Enable ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	writel(A10_SYSMGR_ECC_INTMASK_CLR_L2, sys_manager_base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	       A10_SYSMGR_ECC_INTMASK_CLR_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	writel(A10_MPU_CTRL_L2_ECC_EN, mapped_l2_edac_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	       A10_MPU_CTRL_L2_ECC_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	iounmap(mapped_l2_edac_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }