Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * SMP support for R-Mobile / SH-Mobile - sh73a0 portion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2010  Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2010  Takashi Yoshii
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "sh73a0.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define WUPCR		IOMEM(0xe6151010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SRESCR		IOMEM(0xe6151018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PSTR		IOMEM(0xe6151040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SBAR		IOMEM(0xe6180020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define APARMBAREA	IOMEM(0xe6f10020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SH73A0_SCU_BASE 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	unsigned int lcpu = cpu_logical_map(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	if (((__raw_readl(PSTR) >> (4 * lcpu)) & 3) == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		__raw_writel(1 << lcpu, WUPCR);	/* wake up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		__raw_writel(1 << lcpu, SRESCR);	/* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	/* Map the reset vector (in headsmp.S) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	__raw_writel(0, APARMBAREA);      /* 4k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	__raw_writel(__pa(shmobile_boot_vector), SBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	/* setup sh73a0 specific SCU bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	shmobile_smp_scu_prepare_cpus(SH73A0_SCU_BASE, max_cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) const struct smp_operations sh73a0_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	.smp_prepare_cpus	= sh73a0_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	.smp_boot_secondary	= sh73a0_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	.cpu_can_disable	= shmobile_smp_cpu_can_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	.cpu_die		= shmobile_smp_scu_cpu_die,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	.cpu_kill		= shmobile_smp_scu_cpu_kill,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };