Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * R-Car Generation 2 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013  Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2013  Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2014  Ulrich Hecht
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/dma-map-ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/psci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/secure_cntvoff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "rcar-gen2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static const struct of_device_id cpg_matches[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	{ .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	{ .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	{ .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	{ .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	{ .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	{ .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static unsigned int __init get_extal_freq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct device_node *cpg, *extal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u32 freq = 20000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	int idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	cpg = of_find_matching_node_and_match(NULL, cpg_matches, &match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	if (!cpg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		return freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	if (match->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		idx = of_property_match_string(cpg, "clock-names", match->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	extal = of_parse_phandle(cpg, "clocks", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	of_node_put(cpg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	if (!extal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		return freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	of_property_read_u32(extal, "clock-frequency", &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	of_node_put(extal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CNTCR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CNTFID0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static void __init rcar_gen2_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	bool need_update = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	 * If PSCI is available then most likely we are running on PSCI-enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	 * U-Boot which, we assume, has already taken care of resetting CNTVOFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 * and updating counter module before switching to non-secure mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 * and we don't need to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #ifdef CONFIG_ARM_PSCI_FW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (psci_ops.cpu_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		need_update = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	if (need_update == false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		goto skip_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	secure_cntvoff_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (of_machine_is_compatible("renesas,r8a7745") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	    of_machine_is_compatible("renesas,r8a77470") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	    of_machine_is_compatible("renesas,r8a7792") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	    of_machine_is_compatible("renesas,r8a7794")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		freq = 260000000 / 8;	/* ZS / 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		/* At Linux boot time the r8a7790 arch timer comes up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		 * with the counter disabled. Moreover, it may also report
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		 * a potentially incorrect fixed 13 MHz frequency. To be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		 * correct these registers need to be updated to use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		 * frequency EXTAL / 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		freq = get_extal_freq() / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* Remap "armgcnt address map" space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	base = ioremap(0xe6080000, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 * Update the timer if it is either not running, or is not at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 * right frequency. The timer is only configurable in secure mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 * so this avoids an abort if the loader started the timer and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 * entered the kernel in non-secure mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if ((ioread32(base + CNTCR) & 1) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	    ioread32(base + CNTFID0) != freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		/* Update registers with correct frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		iowrite32(freq, base + CNTFID0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		/* make sure arch timer is started by setting bit 0 of CNTCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		iowrite32(1, base + CNTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) skip_update:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	of_clk_init(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	timer_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct memory_reserve_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u64 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u64 base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				     int depth, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	const __be32 *reg, *endp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	int l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct memory_reserve_config *mrc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	u64 lpae_start = 1ULL << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	/* We are scanning "memory" nodes only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (type == NULL || strcmp(type, "memory"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (reg == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		reg = of_get_flat_dt_prop(node, "reg", &l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (reg == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	endp = reg + (l / sizeof(__be32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		u64 base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		base = dt_mem_next_cell(dt_root_addr_cells, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		size = dt_mem_next_cell(dt_root_size_cells, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		if (base >= lpae_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		if ((base + size) >= lpae_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			size = lpae_start - base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (size < mrc->reserved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		if (base < mrc->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		/* keep the area at top near the 32-bit legacy limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		mrc->base = base + size - mrc->reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		mrc->size = mrc->reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void __init rcar_gen2_reserve(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct memory_reserve_config mrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	/* reserve 256 MiB at the top of the physical legacy 32-bit space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	memset(&mrc, 0, sizeof(mrc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	mrc.reserved = SZ_256M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	of_scan_flat_dt(rcar_gen2_scan_mem, &mrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #ifdef CONFIG_DMA_CMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		static struct cma *rcar_gen2_dma_contiguous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		dma_contiguous_reserve_area(mrc.size, mrc.base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 					    &rcar_gen2_dma_contiguous, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const char * const rcar_gen2_boards_compat_dt[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	"renesas,r8a7790",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	"renesas,r8a7791",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	"renesas,r8a7792",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	"renesas,r8a7793",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	"renesas,r8a7794",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) DT_MACHINE_START(RCAR_GEN2_DT, "Generic R-Car Gen2 (Flattened Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.init_late	= shmobile_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.init_time	= rcar_gen2_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.reserve	= rcar_gen2_reserve,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.dt_compat	= rcar_gen2_boards_compat_dt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const char * const rz_g1_boards_compat_dt[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	"renesas,r8a7742",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	"renesas,r8a7743",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	"renesas,r8a7744",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	"renesas,r8a7745",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	"renesas,r8a77470",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DT_MACHINE_START(RZ_G1_DT, "Generic RZ/G1 (Flattened Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.init_late	= shmobile_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.init_time	= rcar_gen2_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.reserve	= rcar_gen2_reserve,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.dt_compat	= rz_g1_boards_compat_dt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MACHINE_END