^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * r8a7779 processor support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011, 2013 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2013 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "r8a7779.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static struct map_desc r8a7779_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* 2M identity mapping for 0xf0000000 (MPCORE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .virtual = 0xf0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .pfn = __phys_to_pfn(0xf0000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .length = SZ_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .type = MT_DEVICE_NONSHARED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* 16M identity mapping for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .virtual = 0xfe000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .pfn = __phys_to_pfn(0xfe000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .length = SZ_16M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .type = MT_DEVICE_NONSHARED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static void __init r8a7779_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) debug_ll_io_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define INT2SMSKCR0 IOMEM(0xfe7822a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define INT2SMSKCR1 IOMEM(0xfe7822a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define INT2SMSKCR2 IOMEM(0xfe7822a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define INT2SMSKCR3 IOMEM(0xfe7822ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define INT2SMSKCR4 IOMEM(0xfe7822b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define INT2NTSR0 IOMEM(0xfe700060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define INT2NTSR1 IOMEM(0xfe700064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void __init r8a7779_init_irq_dt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) irqchip_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* route all interrupts to ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) __raw_writel(0xffffffff, INT2NTSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __raw_writel(0x3fffffff, INT2NTSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* unmask all known interrupts in INTCS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __raw_writel(0xfffffff0, INT2SMSKCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __raw_writel(0xfff7ffff, INT2SMSKCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __raw_writel(0xfffbffdf, INT2SMSKCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __raw_writel(0xbffffffc, INT2SMSKCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __raw_writel(0x003fee3f, INT2SMSKCR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const char *const r8a7779_compat_dt[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "renesas,r8a7779",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .smp = smp_ops(r8a7779_smp_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .map_io = r8a7779_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .init_irq = r8a7779_init_irq_dt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .init_late = shmobile_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .dt_compat = r8a7779_compat_dt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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