Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * r8a7778 processor support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2013  Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2013  Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define INT2SMSKCR0	0x82288 /* 0xfe782288 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define INT2SMSKCR1	0x8228c /* 0xfe78228c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define INT2NTSR0	0x00018 /* 0xfe700018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define INT2NTSR1	0x0002c /* 0xfe70002c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static void __init r8a7778_init_irq_dt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	void __iomem *base = ioremap(0xfe700000, 0x00100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	BUG_ON(!base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	irqchip_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	/* route all interrupts to ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	__raw_writel(0x73ffffff, base + INT2NTSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	__raw_writel(0xffffffff, base + INT2NTSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	/* unmask all known interrupts in INTCS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	__raw_writel(0x08330773, base + INT2SMSKCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	__raw_writel(0x00311110, base + INT2SMSKCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const char *const r8a7778_compat_dt[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	"renesas,r8a7778",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	.init_early	= shmobile_init_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	.init_irq	= r8a7778_init_irq_dt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	.init_late	= shmobile_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	.dt_compat	= r8a7778_compat_dt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MACHINE_END