^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * R-Car Generation 2 Power management support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 - 2015 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2011 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "rcar-gen2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RST 0xe6160000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CA15BAR 0x0020 /* CA15 Boot Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CA7BAR 0x0030 /* CA7 Boot Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CA15RESCNT 0x0040 /* CA15 Reset Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CA7RESCNT 0x0044 /* CA7 Reset Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* SYS Boot Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SBAR_BAREN BIT(4) /* SBAR is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Reset Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CA15RESCNT_CODE 0xa5a50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CA15RESCNT_CPUS 0xf /* CPU0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CA7RESCNT_CODE 0x5a5a0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CA7RESCNT_CPUS 0xf /* CPU0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* On-chip RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static inline u32 phys_to_sbar(phys_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return (addr >> 8) & 0xfffffc00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void __init rcar_gen2_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) void __iomem *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int once;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) bool has_a7 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) bool has_a15 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (once++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) for_each_of_cpu_node(np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (of_device_is_compatible(np, "arm,cortex-a15"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) has_a15 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) else if (of_device_is_compatible(np, "arm,cortex-a7"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) has_a7 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* No smp-sram in DT, fall back to hardcoded address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) res = (struct resource)DEFINE_RES_MEM(ICRAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) shmobile_boot_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) goto map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) error = of_address_to_resource(np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pr_err("Failed to get smp-sram address: %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* RAM for jump stub, because BAR requires 256KB aligned address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (res.start & (256 * 1024 - 1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) resource_size(&res) < shmobile_boot_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pr_err("Invalid smp-sram region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) p = ioremap(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * install the reset vector, use the largest version if we have enough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * memory available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (resource_size(&res) >= shmobile_boot_size_gen2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) shmobile_boot_cpu_gen2 = read_cpuid_mpidr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) memcpy_toio(p, shmobile_boot_vector_gen2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) shmobile_boot_size_gen2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) iounmap(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* setup reset vectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) p = ioremap(RST, 0x63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bar = phys_to_sbar(res.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (has_a15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel_relaxed(bar, p + CA15BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* de-assert reset for CA15 CPUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel_relaxed((readl_relaxed(p + CA15RESCNT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) p + CA15RESCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (has_a7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) writel_relaxed(bar, p + CA7BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* de-assert reset for CA7 CPUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writel_relaxed((readl_relaxed(p + CA7RESCNT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) p + CA7RESCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) iounmap(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) shmobile_smp_apmu_suspend_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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