^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * SA11x0 Assembler Sleep/WakeUp Management Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * modify it under the terms of the GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * History:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 2001-02-06: Cliff Brake Initial code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 2001-08-29: Nicolas Pitre Simplified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * 2002-05-27: Nicolas Pitre Revisited, more cleanup and simplification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Storage is on the stack now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * sa1100_finish_suspend()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Causes sa11x0 to enter sleep state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Must be aligned to a cacheline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .balign 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ENTRY(sa1100_finish_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) @ disable clock switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) mcr p15, 0, r1, c15, c2, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ldr r6, =MDREFR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ldr r4, [r6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) orr r4, r4, #MDREFR_K1DB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ldr r5, =PPCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) @ Pre-load __loop_udelay into the I-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) mov r0, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) bl __loop_udelay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mov r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) @ The following must all exist in a single cache line to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) @ avoid accessing memory until this sequence is complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) @ otherwise we occasionally hang.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) @ Adjust memory timing before lowering CPU clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) str r4, [r6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) @ delay 90us and set CPU PLL to lowest speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) @ fixes resume problem on high speed SA1110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) mov r0, #90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) bl __loop_udelay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mov r1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) str r1, [r5]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mov r0, #90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) bl __loop_udelay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * SA1110 SDRAM controller workaround. register values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * r0 = &MSC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * r1 = &MSC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * r2 = &MSC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * r3 = MSC0 value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * r4 = MSC1 value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * r5 = MSC2 value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * r6 = &MDREFR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * r7 = first MDREFR value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * r8 = second MDREFR value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * r9 = &MDCNFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * r10 = MDCNFG value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * r11 = third MDREFR value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * r12 = &PMCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * r13 = PMCR value (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ldr r0, =MSC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ldr r1, =MSC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ldr r2, =MSC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ldr r3, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) bic r3, r3, #FMsk(MSC_RT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) bic r3, r3, #FMsk(MSC_RT)<<16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ldr r4, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) bic r4, r4, #FMsk(MSC_RT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bic r4, r4, #FMsk(MSC_RT)<<16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ldr r5, [r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) bic r5, r5, #FMsk(MSC_RT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) bic r5, r5, #FMsk(MSC_RT)<<16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ldr r7, [r6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) bic r7, r7, #0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) bic r7, r7, #0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) orr r8, r7, #MDREFR_SLFRSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ldr r9, =MDCNFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ldr r10, [r9]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bic r11, r8, #MDREFR_SLFRSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bic r11, r11, #MDREFR_E1PIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ldr r12, =PMCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mov r13, #PMCR_SF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) b sa1110_sdram_controller_fix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) sa1110_sdram_controller_fix:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) @ Step 1 clear RT field of all MSCx registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) str r3, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) str r4, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) str r5, [r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) @ Step 2 clear DRI field in MDREFR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) str r7, [r6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) @ Step 3 set SLFRSH bit in MDREFR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) str r8, [r6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) @ Step 4 clear DE bis in MDCNFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) str r10, [r9]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) @ Step 5 clear DRAM refresh control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) str r11, [r6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) @ Wow, now the hardware suspend request pins can be used, that makes them functional for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) @ about 7 ns out of the entire time that the CPU is running!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) @ Step 6 set force sleep bit in PMCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) str r13, [r12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 20: b 20b @ loop waiting for sleep
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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