^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-sa1100/pci-nanoengine.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * PCI functions for BSE nanoEngine PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <mach/nanoengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static void __iomem *nanoengine_pci_map_bus(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned int devfn, int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) if (bus->number != 0 || (devfn >> 3) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) return (void __iomem *)NANO_PCI_CONFIG_SPACE_VIRT +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ((bus->number << 16) | (devfn << 8) | (where & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static struct pci_ops pci_nano_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .map_bus = nanoengine_pci_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .read = pci_generic_config_read32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .write = pci_generic_config_write32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return NANOENGINE_IRQ_GPIO_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static struct resource pci_io_ports =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct resource pci_non_prefetchable_memory = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .name = "PCI non-prefetchable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .start = NANO_PCI_MEM_RW_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* nanoEngine documentation says there is a 1 Megabyte window here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * but PCI reports just 128 + 8 kbytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .end = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* .end = NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * overlaps with previously defined memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Here is what happens:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) # dmesg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pci 0000:00:00.0: reg 14: [io 0x0000-0x003f]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pci 0000:00:00.0: supports D1 D2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pci 0000:00:00.0: PME# disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PCI: bus0: Fast back to back transfers enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pci 0000:00:00.0: BAR 6: can't assign mem pref (size 0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * On the other hand, if we do not request the prefetchable memory resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * linux will alloc it first and the two non-prefetchable memory areas that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * are our real interest will not be mapped. So we choose to map it to an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * unused area. It gets recognized as expansion ROM, but becomes disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Here is what happens then:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) # dmesg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pci 0000:00:00.0: reg 14: [io 0x0000-0x003f]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) pci 0000:00:00.0: supports D1 D2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pci 0000:00:00.0: PME# disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PCI: bus0: Fast back to back transfers enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pci 0000:00:00.0: BAR 6: assigned [mem 0x78000000-0x780fffff pref]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) # lspci -vv -s 0000:00:00.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 00:00.0 Class 0200: Device 8086:1209 (rev 09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR+ <PERR+ INTx-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) Latency: 0 (2000ns min, 14000ns max), Cache Line Size: 32 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) Interrupt: pin A routed to IRQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) Region 0: Memory at 18620000 (32-bit, non-prefetchable) [size=4K]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) Region 1: I/O ports at 0400 [size=64]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) Region 2: [virtual] Memory at 18600000 (32-bit, non-prefetchable) [size=128K]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [virtual] Expansion ROM at 78000000 [disabled] [size=1M]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) Capabilities: [dc] Power Management version 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) Kernel driver in use: e100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) Kernel modules: e100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct resource pci_prefetchable_memory = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .name = "PCI prefetchable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .start = 0x78000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .end = 0x78000000 + NANO_PCI_MEM_RW_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (request_resource(&ioport_resource, &pci_io_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) printk(KERN_ERR "PCI: unable to allocate io port region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (request_resource(&iomem_resource, &pci_non_prefetchable_memory)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) release_resource(&pci_io_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) printk(KERN_ERR "PCI: unable to allocate non prefetchable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (request_resource(&iomem_resource, &pci_prefetchable_memory)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) release_resource(&pci_io_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) release_resource(&pci_non_prefetchable_memory);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pci_add_resource_offset(&sys->resources, &pci_io_ports, sys->io_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pci_add_resource_offset(&sys->resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) &pci_non_prefetchable_memory, sys->mem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pci_add_resource_offset(&sys->resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) &pci_prefetchable_memory, sys->mem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pcibios_min_io = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pcibios_min_mem = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (nr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) sys->io_offset = 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = pci_nanoengine_setup_resources(sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Enable alternate memory bus master mode, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * "Intel StrongARM SA1110 Developer's Manual",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * section 10.8, "Alternate Memory Bus Master Mode". */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) GAFR |= GPIO_MBGNT | GPIO_MBREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) TUCR |= TUCR_MBGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct hw_pci nanoengine_pci __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .map_irq = pci_nanoengine_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .nr_controllers = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .ops = &pci_nano_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .setup = pci_nanoengine_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int __init nanoengine_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (machine_is_nanoengine())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pci_common_init(&nanoengine_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) subsys_initcall(nanoengine_pci_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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