Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * linux/arch/arm/mach-sa1100/neponset.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/gpio/gpio-reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/smc91x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/hardware/sa1111.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <mach/assabet.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <mach/neponset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define NEP_IRQ_SMC91X	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define NEP_IRQ_USAR	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define NEP_IRQ_SA1111	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define NEP_IRQ_NR	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define WHOAMI		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define LEDS		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SWPK		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define IRR		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define KP_Y_IN		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define KP_X_OUT	0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define NCR_0		0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MDM_CTL_0	0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MDM_CTL_1	0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define AUD_CTL		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define IRR_ETHERNET	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define IRR_USAR	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define IRR_SA1111	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define NCR_NGPIO	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MDM_CTL0_NGPIO	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MDM_CTL1_NGPIO	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define AUD_NGPIO	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) extern void sa1110_mb_disable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define to_neponset_gpio_chip(x) container_of(x, struct neponset_gpio_chip, gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static const char *neponset_ncr_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	"gp01_off", "tp_power", "ms_power", "enet_osc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	"spi_kb_wk_up", "a0vpp", "a1vpp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static const char *neponset_mdmctl0_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	"rts3", "dtr3", "rts1", "dtr1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static const char *neponset_mdmctl1_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	"cts3", "dsr3", "dcd3", "cts1", "dsr1", "dcd1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static const char *neponset_aud_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	"sel_1341", "mute_1341",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) struct neponset_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct platform_device *sa1111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct platform_device *smc91x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	unsigned irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct gpio_chip *gpio[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static struct gpiod_lookup_table neponset_uart1_gpio_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.dev_id = "sa11x0-uart.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		GPIO_LOOKUP("neponset-mdm-ctl0", 2, "rts", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		GPIO_LOOKUP("neponset-mdm-ctl0", 3, "dtr", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		GPIO_LOOKUP("neponset-mdm-ctl1", 3, "cts", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		GPIO_LOOKUP("neponset-mdm-ctl1", 4, "dsr", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		GPIO_LOOKUP("neponset-mdm-ctl1", 5, "dcd", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static struct gpiod_lookup_table neponset_uart3_gpio_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.dev_id = "sa11x0-uart.3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		GPIO_LOOKUP("neponset-mdm-ctl0", 0, "rts", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		GPIO_LOOKUP("neponset-mdm-ctl0", 1, "dtr", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		GPIO_LOOKUP("neponset-mdm-ctl1", 0, "cts", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		GPIO_LOOKUP("neponset-mdm-ctl1", 1, "dsr", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		GPIO_LOOKUP("neponset-mdm-ctl1", 2, "dcd", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct gpiod_lookup_table neponset_pcmcia_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.dev_id = "1800",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		GPIO_LOOKUP("sa1111", 1, "a0vcc", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		GPIO_LOOKUP("sa1111", 0, "a1vcc", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		GPIO_LOOKUP("neponset-ncr", 5, "a0vpp", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		GPIO_LOOKUP("neponset-ncr", 6, "a1vpp", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		GPIO_LOOKUP("sa1111", 2, "b0vcc", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		GPIO_LOOKUP("sa1111", 3, "b1vcc", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct neponset_drvdata *nep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void neponset_ncr_frob(unsigned int mask, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct neponset_drvdata *n = nep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	unsigned long m = mask, v = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (nep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		n->gpio[0]->set_multiple(n->gpio[0], &m, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		WARN(1, "nep unset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) EXPORT_SYMBOL(neponset_ncr_frob);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  * Install handler for Neponset IRQ.  Note that we have to loop here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  * since the ETHERNET and USAR IRQs are level based, and we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  * ensure that the IRQ signal is deasserted before returning.  This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  * is rather unfortunate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void neponset_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	unsigned int irr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		 * Acknowledge the parent IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		desc->irq_data.chip->irq_ack(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		 * Read the interrupt reason register.  Let's have all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		 * active IRQ bits high.  Note: there is a typo in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		 * Neponset user's guide for the SA1111 IRR level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		irr = readb_relaxed(d->base + IRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		irr ^= IRR_ETHERNET | IRR_USAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		 * Since there is no individual mask, we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		 * mask the parent IRQ.  This is safe, since we'll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		 * recheck the register for any pending IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		if (irr & (IRR_ETHERNET | IRR_USAR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			desc->irq_data.chip->irq_mask(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			 * Ack the interrupt now to prevent re-entering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			 * this neponset handler.  Again, this is safe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			 * since we'll check the IRR register prior to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			 * leaving.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			desc->irq_data.chip->irq_ack(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			if (irr & IRR_ETHERNET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 				generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			if (irr & IRR_USAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 				generic_handle_irq(d->irq_base + NEP_IRQ_USAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			desc->irq_data.chip->irq_unmask(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		if (irr & IRR_SA1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Yes, we really do not have any kind of masking or unmasking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void nochip_noop(struct irq_data *irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct irq_chip nochip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.name = "neponset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.irq_ack = nochip_noop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.irq_mask = nochip_noop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.irq_unmask = nochip_noop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int neponset_init_gpio(struct gpio_chip **gcp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct device *dev, const char *label, void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	unsigned num, bool in, const char *const * names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	gc = gpio_reg_init(dev, reg, -1, num, label, in ? 0xffffffff : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			   readl_relaxed(reg), names, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (IS_ERR(gc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		return PTR_ERR(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	*gcp = gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct sa1111_platform_data sa1111_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.disable_devs	= SA1111_DEVID_PS2_MSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int neponset_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct neponset_drvdata *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct resource *nep_res, *sa1111_res, *smc91x_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct resource sa1111_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		DEFINE_RES_MEM(0x40000000, SZ_8K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		{ .flags = IORESOURCE_IRQ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct platform_device_info sa1111_devinfo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.parent = &dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.name = "sa1111",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.res = sa1111_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.num_res = ARRAY_SIZE(sa1111_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.data = &sa1111_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		.size_data = sizeof(sa1111_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		.dma_mask = 0xffffffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct resource smc91x_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			0x02000000, "smc91x-regs"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			0x02000000, "smc91x-attrib"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		{ .flags = IORESOURCE_IRQ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct smc91x_platdata smc91x_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		.flags = SMC91X_USE_8BIT | SMC91X_IO_SHIFT_2 | SMC91X_NOWAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	struct platform_device_info smc91x_devinfo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.parent = &dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		.name = "smc91x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		.id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		.res = smc91x_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.num_res = ARRAY_SIZE(smc91x_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.data = &smc91x_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		.size_data = sizeof(smc91x_platdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (nep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	irq = ret = platform_get_irq(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (!nep_res || !smc91x_res || !sa1111_res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	d = kzalloc(sizeof(*d), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (!d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	d->base = ioremap(nep_res->start, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (!d->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		goto err_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (readb_relaxed(d->base + WHOAMI) != 0x11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			 readb_relaxed(d->base + WHOAMI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		goto err_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			NEP_IRQ_NR, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		goto err_irq_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	d->irq_base = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	irq_clear_status_flags(d->irq_base + NEP_IRQ_SMC91X, IRQ_NOREQUEST | IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	irq_clear_status_flags(d->irq_base + NEP_IRQ_USAR, IRQ_NOREQUEST | IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	irq_set_chained_handler_and_data(irq, neponset_irq_handler, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	/* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	neponset_init_gpio(&d->gpio[0], &dev->dev, "neponset-ncr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			   d->base + NCR_0, NCR_NGPIO, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			   neponset_ncr_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	neponset_init_gpio(&d->gpio[1], &dev->dev, "neponset-mdm-ctl0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			   d->base + MDM_CTL_0, MDM_CTL0_NGPIO, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			   neponset_mdmctl0_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	neponset_init_gpio(&d->gpio[2], &dev->dev, "neponset-mdm-ctl1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			   d->base + MDM_CTL_1, MDM_CTL1_NGPIO, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			   neponset_mdmctl1_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	neponset_init_gpio(&d->gpio[3], &dev->dev, "neponset-aud-ctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			   d->base + AUD_CTL, AUD_NGPIO, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			   neponset_aud_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	gpiod_add_lookup_table(&neponset_uart1_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	gpiod_add_lookup_table(&neponset_uart3_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	gpiod_add_lookup_table(&neponset_pcmcia_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	 * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	 * something on the Neponset activates this IRQ on sleep (eth?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	enable_irq_wake(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		 d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	nep = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	/* Ensure that the memory bus request/grant signals are setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	sa1110_mb_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	sa1111_resources[0].parent = sa1111_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	d->sa1111 = platform_device_register_full(&sa1111_devinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	smc91x_resources[0].parent = smc91x_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	smc91x_resources[1].parent = smc91x_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	d->smc91x = platform_device_register_full(&smc91x_devinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	platform_set_drvdata(dev, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)  err_irq_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)  err_id:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	iounmap(d->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)  err_ioremap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	kfree(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)  err_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int neponset_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	struct neponset_drvdata *d = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	int irq = platform_get_irq(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (!IS_ERR(d->sa1111))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		platform_device_unregister(d->sa1111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (!IS_ERR(d->smc91x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		platform_device_unregister(d->smc91x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	gpiod_remove_lookup_table(&neponset_pcmcia_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	gpiod_remove_lookup_table(&neponset_uart3_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	gpiod_remove_lookup_table(&neponset_uart1_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	irq_set_chained_handler(irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	irq_free_descs(d->irq_base, NEP_IRQ_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	nep = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	iounmap(d->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	kfree(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int neponset_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	struct neponset_drvdata *d = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	for (i = 0; i < ARRAY_SIZE(d->gpio); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		ret = gpio_reg_resume(d->gpio[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static const struct dev_pm_ops neponset_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	.resume_noirq = neponset_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	.restore_noirq = neponset_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define PM_OPS &neponset_pm_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static struct platform_driver neponset_device_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	.probe		= neponset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	.remove		= neponset_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		.name	= "neponset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		.pm	= PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int __init neponset_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	return platform_driver_register(&neponset_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) subsys_initcall(neponset_init);