^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-sa1100/nanoengine.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Bright Star Engineering's nanoEngine board init code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_data/sa11x0-serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/root_dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mach/flash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <mach/nanoengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Flash bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct mtd_partition nanoengine_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .name = "nanoEngine boot firmware and parameter table",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .size = 0x00010000, /* 32K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .name = "kernel/initrd reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .size = 0x002f0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .offset = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .name = "experimental filesystem allocation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .size = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .offset = 0x00300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct flash_platform_data nanoengine_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .map_name = "jedec_probe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .parts = nanoengine_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .nr_parts = ARRAY_SIZE(nanoengine_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct resource nanoengine_flash_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static struct map_desc nanoengine_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* System Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .virtual = 0xf0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .pfn = __phys_to_pfn(0x10000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .length = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Internal PCI Memory Read/Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .virtual = NANO_PCI_MEM_RW_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .pfn = __phys_to_pfn(NANO_PCI_MEM_RW_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .length = NANO_PCI_MEM_RW_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Internal PCI Config Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .virtual = NANO_PCI_CONFIG_SPACE_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .pfn = __phys_to_pfn(NANO_PCI_CONFIG_SPACE_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .length = NANO_PCI_CONFIG_SPACE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void __init nanoengine_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) sa1100_map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) iotable_init(nanoengine_io_desc, ARRAY_SIZE(nanoengine_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) sa1100_register_uart(0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) sa1100_register_uart(1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) sa1100_register_uart(2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) Ser1SDCR0 |= SDCR0_UART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* disable IRDA -- UART2 is used as a normal serial port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) Ser2UTCR4 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) Ser2HSCR0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct gpiod_lookup_table nanoengine_pcmcia0_gpio_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .dev_id = "sa11x0-pcmcia.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) GPIO_LOOKUP("gpio", 11, "ready", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) GPIO_LOOKUP("gpio", 13, "detect", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) GPIO_LOOKUP("gpio", 15, "reset", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct gpiod_lookup_table nanoengine_pcmcia1_gpio_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .dev_id = "sa11x0-pcmcia.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) GPIO_LOOKUP("gpio", 12, "ready", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) GPIO_LOOKUP("gpio", 14, "detect", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) GPIO_LOOKUP("gpio", 16, "reset", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void __init nanoengine_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) sa11x0_register_pcmcia(0, &nanoengine_pcmcia0_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) sa11x0_register_pcmcia(1, &nanoengine_pcmcia1_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) sa11x0_register_mtd(&nanoengine_flash_data, nanoengine_flash_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ARRAY_SIZE(nanoengine_flash_resources));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MACHINE_START(NANOENGINE, "BSE nanoEngine")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .map_io = nanoengine_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .nr_irqs = SA1100_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .init_irq = sa1100_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .init_time = sa1100_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .init_machine = nanoengine_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .init_late = sa11x0_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .restart = sa11x0_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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