Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * linux/arch/arm/mach-sa1100/jornada720.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * HP Jornada720 init code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  Copyright (C) 2005 Michael Gernoth <michael@gernoth.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/platform_data/sa11x0-serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <video/s1d13xxxfb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/hardware/sa1111.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <asm/mach/flash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * HP Documentation referred in this file:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* line 110 of HP's doc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TUCR_VAL	0x20000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* memory space (line 52 of HP's doc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SA1111REGSTART	0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SA1111REGLEN	0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define EPSONREGSTART	0x48000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define EPSONREGLEN	0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define EPSONFBSTART	0x48200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* 512kB framebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define EPSONFBLEN	512*1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	/* line 344 of HP's doc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{0x0001,0x00},	// Miscellaneous Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{0x01FC,0x00},	// Display Mode Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{0x0004,0x00},	// General IO Pins Configuration Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{0x0005,0x00},	// General IO Pins Configuration Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{0x0008,0x00},	// General IO Pins Control Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{0x0009,0x00},	// General IO Pins Control Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{0x0010,0x01},	// Memory Clock Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	{0x0014,0x11},	// LCD Pixel Clock Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{0x0018,0x01},	// CRT/TV Pixel Clock Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	{0x001C,0x01},	// MediaPlug Clock Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	{0x001E,0x01},	// CPU To Memory Wait State Select Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	{0x0020,0x00},	// Memory Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	{0x0021,0x45},	// DRAM Refresh Rate Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	{0x002A,0x01},	// DRAM Timings Control Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	{0x002B,0x03},	// DRAM Timings Control Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	{0x0030,0x1c},	// Panel Type Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	{0x0031,0x00},	// MOD Rate Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	{0x0032,0x4F},	// LCD Horizontal Display Width Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	{0x0034,0x07},	// LCD Horizontal Non-Display Period Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	{0x0035,0x01},	// TFT FPLINE Start Position Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	{0x0036,0x0B},	// TFT FPLINE Pulse Width Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	{0x0038,0xEF},	// LCD Vertical Display Height Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	{0x0039,0x00},	// LCD Vertical Display Height Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{0x003A,0x13},	// LCD Vertical Non-Display Period Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{0x003B,0x0B},	// TFT FPFRAME Start Position Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{0x003C,0x01},	// TFT FPFRAME Pulse Width Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	{0x0040,0x05},	// LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{0x0041,0x00},	// LCD Miscellaneous Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{0x0042,0x00},	// LCD Display Start Address Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	{0x0043,0x00},	// LCD Display Start Address Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	{0x0044,0x00},	// LCD Display Start Address Register 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	{0x0046,0x80},	// LCD Memory Address Offset Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{0x0047,0x02},	// LCD Memory Address Offset Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{0x0048,0x00},	// LCD Pixel Panning Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{0x004A,0x00},	// LCD Display FIFO High Threshold Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{0x004B,0x00},	// LCD Display FIFO Low Threshold Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	{0x0050,0x4F},	// CRT/TV Horizontal Display Width Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	{0x0052,0x13},	// CRT/TV Horizontal Non-Display Period Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	{0x0053,0x01},	// CRT/TV HRTC Start Position Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	{0x0054,0x0B},	// CRT/TV HRTC Pulse Width Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	{0x0056,0xDF},	// CRT/TV Vertical Display Height Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	{0x0057,0x01},	// CRT/TV Vertical Display Height Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	{0x0058,0x2B},	// CRT/TV Vertical Non-Display Period Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{0x0059,0x09},	// CRT/TV VRTC Start Position Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	{0x005A,0x01},	// CRT/TV VRTC Pulse Width Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	{0x005B,0x10},	// TV Output Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	{0x0060,0x03},	// CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	{0x0062,0x00},	// CRT/TV Display Start Address Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{0x0063,0x00},	// CRT/TV Display Start Address Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{0x0064,0x00},	// CRT/TV Display Start Address Register 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	{0x0066,0x40},	// CRT/TV Memory Address Offset Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{0x0067,0x01},	// CRT/TV Memory Address Offset Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{0x0068,0x00},	// CRT/TV Pixel Panning Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{0x006A,0x00},	// CRT/TV Display FIFO High Threshold Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	{0x006B,0x00},	// CRT/TV Display FIFO Low Threshold Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	{0x0070,0x00},	// LCD Ink/Cursor Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	{0x0071,0x01},	// LCD Ink/Cursor Start Address Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	{0x0072,0x00},	// LCD Cursor X Position Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	{0x0073,0x00},	// LCD Cursor X Position Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	{0x0074,0x00},	// LCD Cursor Y Position Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	{0x0075,0x00},	// LCD Cursor Y Position Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	{0x0076,0x00},	// LCD Ink/Cursor Blue Color 0 Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	{0x0077,0x00},	// LCD Ink/Cursor Green Color 0 Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{0x0078,0x00},	// LCD Ink/Cursor Red Color 0 Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	{0x007A,0x1F},	// LCD Ink/Cursor Blue Color 1 Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	{0x007B,0x3F},	// LCD Ink/Cursor Green Color 1 Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	{0x007C,0x1F},	// LCD Ink/Cursor Red Color 1 Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{0x007E,0x00},	// LCD Ink/Cursor FIFO Threshold Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	{0x0080,0x00},	// CRT/TV Ink/Cursor Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{0x0081,0x01},	// CRT/TV Ink/Cursor Start Address Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{0x0082,0x00},	// CRT/TV Cursor X Position Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{0x0083,0x00},	// CRT/TV Cursor X Position Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{0x0084,0x00},	// CRT/TV Cursor Y Position Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{0x0085,0x00},	// CRT/TV Cursor Y Position Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{0x0086,0x00},	// CRT/TV Ink/Cursor Blue Color 0 Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{0x0087,0x00},	// CRT/TV Ink/Cursor Green Color 0 Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{0x0088,0x00},	// CRT/TV Ink/Cursor Red Color 0 Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{0x008A,0x1F},	// CRT/TV Ink/Cursor Blue Color 1 Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	{0x008B,0x3F},	// CRT/TV Ink/Cursor Green Color 1 Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{0x008C,0x1F},	// CRT/TV Ink/Cursor Red Color 1 Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	{0x008E,0x00},	// CRT/TV Ink/Cursor FIFO Threshold Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	{0x0100,0x00},	// BitBlt Control Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	{0x0101,0x00},	// BitBlt Control Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	{0x0102,0x00},	// BitBlt ROP Code/Color Expansion Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	{0x0103,0x00},	// BitBlt Operation Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	{0x0104,0x00},	// BitBlt Source Start Address Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	{0x0105,0x00},	// BitBlt Source Start Address Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	{0x0106,0x00},	// BitBlt Source Start Address Register 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	{0x0108,0x00},	// BitBlt Destination Start Address Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	{0x0109,0x00},	// BitBlt Destination Start Address Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	{0x010A,0x00},	// BitBlt Destination Start Address Register 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	{0x010C,0x00},	// BitBlt Memory Address Offset Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	{0x010D,0x00},	// BitBlt Memory Address Offset Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	{0x0110,0x00},	// BitBlt Width Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	{0x0111,0x00},	// BitBlt Width Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	{0x0112,0x00},	// BitBlt Height Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{0x0113,0x00},	// BitBlt Height Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{0x0114,0x00},	// BitBlt Background Color Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	{0x0115,0x00},	// BitBlt Background Color Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	{0x0118,0x00},	// BitBlt Foreground Color Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	{0x0119,0x00},	// BitBlt Foreground Color Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	{0x01E0,0x00},	// Look-Up Table Mode Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{0x01E2,0x00},	// Look-Up Table Address Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	/* not sure, wouldn't like to mess with the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	{0x01E4,0x00},	// Look-Up Table Data Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/* jornada doc says 0x00, but I trust the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	{0x01F0,0x10},	// Power Save Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	{0x01F1,0x00},	// Power Save Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	{0x01F4,0x00},	// CPU-to-Memory Access Watchdog Timer Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	{0x01FC,0x01},	// Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.initregs		= s1d13xxxfb_initregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.initregssize		= ARRAY_SIZE(s1d13xxxfb_initregs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.platform_init_video	= NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct resource s1d13xxxfb_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	[0] = DEFINE_RES_MEM(EPSONFBSTART, EPSONFBLEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	[1] = DEFINE_RES_MEM(EPSONREGSTART, EPSONREGLEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct platform_device s1d13xxxfb_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.name		= S1D_DEVICENAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.id		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.dev		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		.platform_data	= &s1d13xxxfb_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.num_resources	= ARRAY_SIZE(s1d13xxxfb_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.resource	= s1d13xxxfb_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct gpiod_lookup_table jornada_pcmcia_gpiod_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.dev_id = "1800",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		GPIO_LOOKUP("sa1111", 0, "s0-power", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		GPIO_LOOKUP("sa1111", 1, "s1-power", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		GPIO_LOOKUP("sa1111", 2, "s0-3v", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		GPIO_LOOKUP("sa1111", 3, "s1-3v", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct resource sa1111_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	[0] = DEFINE_RES_MEM(SA1111REGSTART, SA1111REGLEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	[1] = DEFINE_RES_IRQ(IRQ_GPIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static struct sa1111_platform_data sa1111_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.disable_devs	= SA1111_DEVID_PS2_MSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static u64 sa1111_dmamask = 0xffffffffUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct platform_device sa1111_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.name		= "sa1111",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.id		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.dev		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.dma_mask = &sa1111_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.coherent_dma_mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.platform_data = &sa1111_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.num_resources	= ARRAY_SIZE(sa1111_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.resource	= sa1111_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static struct platform_device jornada_ssp_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.name           = "jornada_ssp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.id             = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct resource jornada_kbd_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	DEFINE_RES_IRQ(IRQ_GPIO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct platform_device jornada_kbd_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.name		= "jornada720_kbd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.id		= -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.num_resources	= ARRAY_SIZE(jornada_kbd_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.resource	= jornada_kbd_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct gpiod_lookup_table jornada_ts_gpiod_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.dev_id		= "jornada_ts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.table		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		GPIO_LOOKUP("gpio", 9, "penup", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct platform_device jornada_ts_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.name		= "jornada_ts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.id		= -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct platform_device *devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	&sa1111_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	&jornada_ssp_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	&s1d13xxxfb_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	&jornada_kbd_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	&jornada_ts_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int __init jornada720_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (machine_is_jornada720()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		/* we want to use gpio20 as input to drive the clock of our uart 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		GPDR |= GPIO_GPIO20;	/* Clear gpio20 pin as input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		TUCR = TUCR_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		GPSR = GPIO_GPIO20;	/* start gpio20 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		GPCR = GPIO_GPIO20;	/* stop gpio20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		GPSR = GPIO_GPIO20;	/* restart gpio20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		udelay(20);		/* give it some time to restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		gpiod_add_lookup_table(&jornada_ts_gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		gpiod_add_lookup_table(&jornada_pcmcia_gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) arch_initcall(jornada720_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static struct map_desc jornada720_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	{	/* Epson registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.virtual	= 0xf0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		.pfn		= __phys_to_pfn(EPSONREGSTART),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.length		= EPSONREGLEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.type		= MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}, {	/* Epson frame buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.virtual	= 0xf1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.pfn		= __phys_to_pfn(EPSONFBSTART),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.length		= EPSONFBLEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.type		= MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static void __init jornada720_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	sa1100_map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	sa1100_register_uart(0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	sa1100_register_uart(1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static struct mtd_partition jornada720_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.name		= "JORNADA720 boot firmware",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.size		= 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		.offset		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		.mask_flags	= MTD_WRITEABLE, /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		.name		= "JORNADA720 kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		.size		= 0x000c0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		.offset		= 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		.name		= "JORNADA720 params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		.size		= 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		.offset		= 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		.name		= "JORNADA720 initrd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		.size		= 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.offset		= 0x00140000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		.name		= "JORNADA720 root cramfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		.size		= 0x00300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		.offset		= 0x00240000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		.name		= "JORNADA720 usr cramfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		.size		= 0x00800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		.offset		= 0x00540000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		.name		= "JORNADA720 usr local",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		.size		= 0, /* will expand to the end of the flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		.offset		= 0x00d00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void jornada720_set_vpp(int vpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (vpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		/* enabling flash write (line 470 of HP's doc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		PPSR |= PPC_LDD7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		/* disabling flash write (line 470 of HP's doc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		PPSR &= ~PPC_LDD7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	PPDR |= PPC_LDD7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static struct flash_platform_data jornada720_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	.map_name	= "cfi_probe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	.set_vpp	= jornada720_set_vpp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	.parts		= jornada720_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	.nr_parts	= ARRAY_SIZE(jornada720_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static struct resource jornada720_flash_resource =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void __init jornada720_mach_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	sa11x0_register_mtd(&jornada720_flash_data, &jornada720_flash_resource, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MACHINE_START(JORNADA720, "HP Jornada 720")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	/* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	.atag_offset	= 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	.map_io		= jornada720_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.nr_irqs	= SA1100_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.init_irq	= sa1100_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.init_time	= sa1100_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	.init_machine	= jornada720_mach_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	.init_late	= sa11x0_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #ifdef CONFIG_SA1111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	.dma_zone_size	= SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	.restart	= sa11x0_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MACHINE_END