^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-sa1100/generic.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Code common to all SA11x0 machines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regulator/fixed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irqchip/irq-sa11x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <video/sa1100fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <soc/sa1100/pwer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/mach/flash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/system_misc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <mach/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <clocksource/pxa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int reset_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) EXPORT_SYMBOL(reset_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NR_FREQS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * This table is setup for a 3.6864MHz Crystal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct cpufreq_frequency_table sa11x0_freq_table[NR_FREQS+1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { .frequency = 59000, /* 59.0 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { .frequency = 73700, /* 73.7 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { .frequency = 88500, /* 88.5 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { .frequency = 103200, /* 103.2 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { .frequency = 118000, /* 118.0 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { .frequency = 132700, /* 132.7 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { .frequency = 147500, /* 147.5 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .frequency = 162200, /* 162.2 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { .frequency = 176900, /* 176.9 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { .frequency = 191700, /* 191.7 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { .frequency = 206400, /* 206.4 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { .frequency = 221200, /* 221.2 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { .frequency = 235900, /* 235.9 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { .frequency = 250700, /* 250.7 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { .frequency = 265400, /* 265.4 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { .frequency = 280200, /* 280.2 MHz */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { .frequency = CPUFREQ_TABLE_END, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int sa11x0_getspeed(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return sa11x0_freq_table[PPCR & 0xf].frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Default power-off for SA1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void sa1100_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* disable internal oscillator, float CS lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* enable wake-up on GPIO0 (Assabet...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PWER = GFER = GRER = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * set scratchpad to zero, just in case it is used as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * restart address by the bootloader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PSPR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* enter sleep mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PMCR = PMCR_SF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void sa11x0_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clear_reset_status(RESET_STATUS_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (mode == REBOOT_SOFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Jump into ROM at address 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) soft_restart(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Use on-chip reset capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) RSRR = RSRR_SWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void sa11x0_register_device(struct platform_device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dev->dev.platform_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) err = platform_device_register(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) printk(KERN_ERR "Unable to register device %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev->name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct resource sa11x0udc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static u64 sa11x0udc_dma_mask = 0xffffffffUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct platform_device sa11x0udc_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .name = "sa11x0-udc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .dma_mask = &sa11x0udc_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .coherent_dma_mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .num_resources = ARRAY_SIZE(sa11x0udc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .resource = sa11x0udc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct resource sa11x0uart1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct platform_device sa11x0uart1_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "sa11x0-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .num_resources = ARRAY_SIZE(sa11x0uart1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .resource = sa11x0uart1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct resource sa11x0uart3_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct platform_device sa11x0uart3_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .name = "sa11x0-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .id = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .num_resources = ARRAY_SIZE(sa11x0uart3_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .resource = sa11x0uart3_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct resource sa11x0mcp_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct platform_device sa11x0mcp_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .name = "sa11x0-mcp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .dma_mask = &sa11x0mcp_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .coherent_dma_mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .num_resources = ARRAY_SIZE(sa11x0mcp_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .resource = sa11x0mcp_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void __init sa11x0_ppc_configure_mcp(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Setup the PPC unit for the MCP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PPDR &= ~PPC_RXD4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PSDR |= PPC_RXD4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) void sa11x0_register_mcp(struct mcp_plat_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) sa11x0_register_device(&sa11x0mcp_device, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct resource sa11x0ssp_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) [0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static struct platform_device sa11x0ssp_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .name = "sa11x0-ssp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .dma_mask = &sa11x0ssp_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .coherent_dma_mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .num_resources = ARRAY_SIZE(sa11x0ssp_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .resource = sa11x0ssp_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static struct resource sa11x0fb_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [1] = DEFINE_RES_IRQ(IRQ_LCD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static struct platform_device sa11x0fb_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .name = "sa11x0-fb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .coherent_dma_mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .num_resources = ARRAY_SIZE(sa11x0fb_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .resource = sa11x0fb_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) sa11x0_register_device(&sa11x0fb_device, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void sa11x0_register_pcmcia(int socket, struct gpiod_lookup_table *table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) gpiod_add_lookup_table(table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) platform_device_register_simple("sa11x0-pcmcia", socket, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static struct platform_device sa11x0mtd_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .name = "sa1100-mtd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) void sa11x0_register_mtd(struct flash_platform_data *flash,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct resource *res, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) flash->name = "sa1100";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) sa11x0mtd_device.resource = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) sa11x0mtd_device.num_resources = nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) sa11x0_register_device(&sa11x0mtd_device, flash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static struct resource sa11x0ir_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DEFINE_RES_IRQ(IRQ_Ser2ICP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct platform_device sa11x0ir_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .name = "sa11x0-ir",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .num_resources = ARRAY_SIZE(sa11x0ir_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .resource = sa11x0ir_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) void sa11x0_register_irda(struct irda_platform_data *irda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) sa11x0_register_device(&sa11x0ir_device, irda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct resource sa1100_rtc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DEFINE_RES_MEM(0x90010000, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static struct platform_device sa11x0rtc_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .name = "sa1100-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .num_resources = ARRAY_SIZE(sa1100_rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .resource = sa1100_rtc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct resource sa11x0dma_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DEFINE_RES_IRQ(IRQ_DMA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) DEFINE_RES_IRQ(IRQ_DMA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) DEFINE_RES_IRQ(IRQ_DMA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) DEFINE_RES_IRQ(IRQ_DMA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) DEFINE_RES_IRQ(IRQ_DMA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) DEFINE_RES_IRQ(IRQ_DMA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct platform_device sa11x0dma_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .name = "sa11x0-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .dma_mask = &sa11x0dma_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .coherent_dma_mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .num_resources = ARRAY_SIZE(sa11x0dma_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .resource = sa11x0dma_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static struct platform_device *sa11x0_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) &sa11x0udc_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) &sa11x0uart1_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) &sa11x0uart3_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) &sa11x0ssp_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) &sa11x0rtc_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) &sa11x0dma_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int __init sa1100_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) pm_power_off = sa1100_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) regulator_has_full_constraints();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) arch_initcall(sa1100_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) void __init sa11x0_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) sa11x0_pm_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int __init sa11x0_register_fixed_regulator(int n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct fixed_voltage_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct regulator_consumer_supply *supplies, unsigned num_supplies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) bool uses_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct regulator_init_data *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) cfg->init_data = id = kzalloc(sizeof(*cfg->init_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!cfg->init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (!uses_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) id->constraints.always_on = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) id->constraints.name = cfg->supply_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) id->constraints.min_uV = cfg->microvolts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) id->constraints.max_uV = cfg->microvolts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) id->constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) id->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) id->consumer_supplies = supplies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) id->num_consumer_supplies = num_supplies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) platform_device_register_resndata(NULL, "reg-fixed-voltage", n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) NULL, 0, cfg, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Common I/O mapping:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Typically, static virtual address mappings are as follow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * 0xf4000000-0xf4ffffff: SA-1111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * 0xf5000000-0xf5ffffff: reserved (used by cache flushing area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * 0xffff0000-0xffff0fff: SA1100 exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * 0xffff2000-0xffff2fff: Minicache copy_user_page area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * Below 0xe8000000 is reserved for vm allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * The machine specific code must provide the extra mapping beside the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * default mapping provided here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static struct map_desc standard_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { /* PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .virtual = 0xf8000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .pfn = __phys_to_pfn(0x80000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .length = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }, { /* SCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .virtual = 0xfa000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .pfn = __phys_to_pfn(0x90000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .length = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }, { /* MER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .virtual = 0xfc000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .pfn = __phys_to_pfn(0xa0000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .length = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }, { /* LCD + DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .virtual = 0xfe000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .pfn = __phys_to_pfn(0xb0000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .length = 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) void __init sa1100_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) void __init sa1100_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct resource irq_resource =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) void __init sa1100_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) request_resource(&iomem_resource, &irq_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) sa11x0_init_irq_nodt(IRQ_GPIO0_SC, irq_resource.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) sa1100_init_gpio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) sa11xx_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * Disable the memory bus request/grant signals on the SA1110 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * ensure that we don't receive spurious memory requests. We set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * the MBGNT signal false to ensure the SA1111 doesn't own the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * SDRAM bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) void sa1110_mb_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PGSR &= ~GPIO_MBGNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) GPCR = GPIO_MBGNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * If the system is going to use the SA-1111 DMA engines, set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * the memory bus request/grant pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) void sa1110_mb_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PGSR &= ~GPIO_MBGNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) GPCR = GPIO_MBGNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) TUCR |= TUCR_MR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PWER |= BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PWER &= ~BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int sa11x0_sc_set_wake(unsigned int irq, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (BIT(irq) != IC_RTCAlrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PWER |= PWER_RTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PWER &= ~PWER_RTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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