^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-sa1100/assabet.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file contains all Assabet-specific tweaks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/gpio-reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio_keys.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_data/sa11x0-serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/fixed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/ucb1x00.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <video/sa1100fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/pgtable-hwdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/mach/flash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/platform_data/irda-sa11x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <mach/assabet.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/platform_data/mfd-mcp-sa11x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ASSABET_BCR_DB1110 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) (ASSABET_BCR_SPK_OFF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ASSABET_BCR_IRDA_MD0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ASSABET_BCR_DB1111 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (ASSABET_BCR_SPK_OFF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ASSABET_BCR_IRDA_MD0 | ASSABET_BCR_CF_RST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long SCR_value = ASSABET_SCR_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) EXPORT_SYMBOL(SCR_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct gpio_chip *assabet_bcr_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const char *assabet_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "cf_pwr", "cf_gfx_reset", "nsoft_reset", "irda_fsel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "irda_md0", "irda_md1", "stereo_loopback", "ncf_bus_on",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "audio_pwr_on", "light_pwr_on", "lcd16data", "lcd_pwr_on",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "rs232_on", "nred_led", "ngreen_led", "vib_on",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "com_dtr", "com_rts", "radio_wake_mod", "i2c_enab",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "tvir_enab", "qmute", "radio_pwr_on", "spkr_off",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "rs232_valid", "com_dcd", "com_cts", "com_dsr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "radio_cts", "radio_dsr", "radio_dcd", "radio_ri",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* The old deprecated interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void ASSABET_BCR_frob(unsigned int mask, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned long m = mask, v = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) assabet_bcr_gc->set_multiple(assabet_bcr_gc, &m, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) EXPORT_SYMBOL(ASSABET_BCR_frob);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int __init assabet_init_gpio(void __iomem *reg, u32 def_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writel_relaxed(def_val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) gc = gpio_reg_init(NULL, reg, -1, 32, "assabet", 0xff000000, def_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) assabet_names, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (IS_ERR(gc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return PTR_ERR(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) assabet_bcr_gc = gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return gc->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * The codec reset goes to three devices, so we need to release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * the rest when any one of these requests it. However, that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * causes the ADV7171 to consume around 100mA - more than half
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * the LCD-blanked power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * With the ADV7171, LCD and backlight enabled, we go over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * budget on the MAX846 Li-Ion charger, and if no Li-Ion battery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * is connected, the Assabet crashes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RST_UCB1X00 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RST_UDA1341 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RST_ADV7171 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SDA GPIO_GPIO(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SCK GPIO_GPIO(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MOD GPIO_GPIO(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void adv7171_start(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) GPSR = SCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) GPSR = SDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) GPCR = SDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void adv7171_stop(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) GPSR = SCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) GPSR = SDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void adv7171_send(unsigned byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for (i = 0; i < 8; i++, byte <<= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) GPCR = SCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (byte & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) GPSR = SDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) GPCR = SDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) GPSR = SCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) GPCR = SCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) GPSR = SDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) GPDR &= ~SDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) GPSR = SCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (GPLR & SDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) printk(KERN_WARNING "No ACK from ADV7171\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) GPCR = SCK | SDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) GPDR |= SDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void adv7171_write(unsigned reg, unsigned val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned gpdr = GPDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned gplr = GPLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ASSABET_BCR_frob(ASSABET_BCR_AUDIO_ON, ASSABET_BCR_AUDIO_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) GPCR = SDA | SCK | MOD; /* clear L3 mode to ensure UDA1341 doesn't respond */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) GPDR = (GPDR | SCK | MOD) & ~SDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (!(GPLR & SDA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) printk(KERN_WARNING "Something dragging SDA down?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) GPDR |= SDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) adv7171_start();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) adv7171_send(0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) adv7171_send(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) adv7171_send(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) adv7171_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Restore GPIO state for L3 bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) GPSR = gplr & (SDA | SCK | MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) GPCR = (~gplr) & (SDA | SCK | MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) GPDR = gpdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void adv7171_sleep(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Put the ADV7171 into sleep mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) adv7171_write(0x04, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static unsigned codec_nreset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void assabet_codec_reset(unsigned mask, int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bool old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) old = !codec_nreset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) codec_nreset &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) codec_nreset |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (old != !codec_nreset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (codec_nreset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ASSABET_BCR_set(ASSABET_BCR_NCODEC_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) adv7171_sleep();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ASSABET_BCR_clear(ASSABET_BCR_NCODEC_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void assabet_ucb1x00_reset(enum ucb1x00_reset state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int set = state == UCB_RST_REMOVE || state == UCB_RST_SUSPEND ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) state == UCB_RST_PROBE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) assabet_codec_reset(RST_UCB1X00, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void assabet_uda1341_reset(int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) assabet_codec_reset(RST_UDA1341, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) EXPORT_SYMBOL(assabet_uda1341_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Assabet flash support code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #ifdef ASSABET_REV_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * Phase 4 Assabet has two 28F160B3 flash parts in bank 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct mtd_partition assabet_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .name = "bootloader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .size = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .name = "bootloader params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .size = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .name = "jffs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Phase 5 Assabet has two 28F128J3A flash parts in bank 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct mtd_partition assabet_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .name = "bootloader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .size = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .name = "bootloader params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .size = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .name = "jffs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static struct flash_platform_data assabet_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .map_name = "cfi_probe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .parts = assabet_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .nr_parts = ARRAY_SIZE(assabet_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static struct resource assabet_flash_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Assabet IrDA support code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int assabet_irda_set_power(struct device *dev, unsigned int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static unsigned int bcr_state[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ASSABET_BCR_IRDA_MD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ASSABET_BCR_IRDA_MD1|ASSABET_BCR_IRDA_MD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ASSABET_BCR_IRDA_MD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (state < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ASSABET_BCR_frob(ASSABET_BCR_IRDA_MD1 | ASSABET_BCR_IRDA_MD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) bcr_state[state]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void assabet_irda_set_speed(struct device *dev, unsigned int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (speed < 4000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ASSABET_BCR_clear(ASSABET_BCR_IRDA_FSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ASSABET_BCR_set(ASSABET_BCR_IRDA_FSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static struct irda_platform_data assabet_irda_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .set_power = assabet_irda_set_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .set_speed = assabet_irda_set_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct ucb1x00_plat_data assabet_ucb1x00_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .reset = assabet_ucb1x00_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .gpio_base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .can_wakeup = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct mcp_plat_data assabet_mcp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .mccr0 = MCCR0_ADM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .sclk_rate = 11981000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .codec_pdata = &assabet_ucb1x00_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void assabet_lcd_set_visual(u32 visual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u_int is_true_color = visual == FB_VISUAL_TRUECOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (machine_is_assabet()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #if 1 // phase 4 or newer Assabet's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (is_true_color)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) // older Assabet's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (is_true_color)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #ifndef ASSABET_PAL_VIDEO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static void assabet_lcd_backlight_power(int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * Turn on/off the backlight. When turning the backlight on, we wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * 500us after turning it on so we don't cause the supplies to droop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * when we enable the LCD controller (and cause a hard reset.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void assabet_lcd_power(int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ASSABET_BCR_set(ASSABET_BCR_LCD_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) udelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * The assabet uses a sharp LQ039Q2DS54 LCD module. It is actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * takes an RGB666 signal, but we provide it with an RGB565 signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * instead (def_rgb_16).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static struct sa1100fb_mach_info lq039q2ds54_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .pixclock = 171521, .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .xres = 320, .yres = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .hsync_len = 5, .vsync_len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .left_margin = 61, .upper_margin = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .right_margin = 9, .lower_margin = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .backlight_power = assabet_lcd_backlight_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .lcd_power = assabet_lcd_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .set_visual = assabet_lcd_set_visual,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static void assabet_pal_backlight_power(int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static void assabet_pal_power(int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct sa1100fb_mach_info pal_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .pixclock = 67797, .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .xres = 640, .yres = 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .hsync_len = 64, .vsync_len = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .left_margin = 125, .upper_margin = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .right_margin = 115, .lower_margin = 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .backlight_power = assabet_pal_backlight_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .lcd_power = assabet_pal_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .set_visual = assabet_lcd_set_visual,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #ifdef CONFIG_ASSABET_NEPONSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static struct resource neponset_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) DEFINE_RES_MEM(0x10000000, 0x08000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) DEFINE_RES_MEM(0x18000000, 0x04000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) DEFINE_RES_MEM(0x40000000, SZ_8K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DEFINE_RES_IRQ(IRQ_GPIO25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static struct gpiod_lookup_table assabet_cf_gpio_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .dev_id = "sa11x0-pcmcia.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) GPIO_LOOKUP("gpio", 21, "ready", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) GPIO_LOOKUP("gpio", 22, "detect", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) GPIO_LOOKUP("gpio", 24, "bvd2", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) GPIO_LOOKUP("gpio", 25, "bvd1", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) GPIO_LOOKUP("assabet", 1, "reset", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) GPIO_LOOKUP("assabet", 7, "bus-enable", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static struct regulator_consumer_supply assabet_cf_vcc_consumers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) REGULATOR_SUPPLY("vcc", "sa11x0-pcmcia.1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static struct fixed_voltage_config assabet_cf_vcc_pdata __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .supply_name = "cf-power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .microvolts = 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static struct gpiod_lookup_table assabet_cf_vcc_gpio_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .dev_id = "reg-fixed-voltage.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) GPIO_LOOKUP("assabet", 0, NULL, GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static struct gpio_led assabet_leds[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .name = "assabet:red",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .default_trigger = "cpu0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .active_low = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .default_state = LEDS_GPIO_DEFSTATE_KEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .name = "assabet:green",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .default_trigger = "heartbeat",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .active_low = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .default_state = LEDS_GPIO_DEFSTATE_KEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const struct gpio_led_platform_data assabet_leds_pdata __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .num_leds = ARRAY_SIZE(assabet_leds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .leds = assabet_leds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static struct gpio_keys_button assabet_keys_buttons[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .gpio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .irq = IRQ_GPIO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .desc = "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .wakeup = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .can_disable = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .debounce_interval = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .gpio = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .irq = IRQ_GPIO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .desc = "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .wakeup = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .can_disable = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .debounce_interval = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static const struct gpio_keys_platform_data assabet_keys_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .buttons = assabet_keys_buttons,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .nbuttons = ARRAY_SIZE(assabet_keys_buttons),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .rep = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static struct gpiod_lookup_table assabet_uart1_gpio_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .dev_id = "sa11x0-uart.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) GPIO_LOOKUP("assabet", 16, "dtr", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) GPIO_LOOKUP("assabet", 17, "rts", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) GPIO_LOOKUP("assabet", 25, "dcd", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GPIO_LOOKUP("assabet", 26, "cts", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) GPIO_LOOKUP("assabet", 27, "dsr", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static struct gpiod_lookup_table assabet_uart3_gpio_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .dev_id = "sa11x0-uart.3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) GPIO_LOOKUP("assabet", 28, "cts", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) GPIO_LOOKUP("assabet", 29, "dsr", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) GPIO_LOOKUP("assabet", 30, "dcd", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) GPIO_LOOKUP("assabet", 31, "rng", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void __init assabet_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * Ensure that the power supply is in "high power" mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GPSR = GPIO_GPIO16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) GPDR |= GPIO_GPIO16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * Ensure that these pins are set as outputs and are driving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * logic 0. This ensures that we won't inadvertently toggle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * the WS latch in the CPLD, and we don't float causing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * excessive power drain. --rmk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * Also set GPIO27 as an output; this is used to clock UART3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * via the FPGA and as otherwise has no pullups or pulldowns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * so stop it floating.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GPCR = GPIO_GPIO27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) GPDR |= GPIO_GPIO27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * Set up registers for sleep mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PWER = PWER_GPIO0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) PGSR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PCFR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PSDR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PPDR |= PPC_TXD3 | PPC_TXD1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PPSR |= PPC_TXD3 | PPC_TXD1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) sa11x0_ppc_configure_mcp();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (machine_has_neponset()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #ifndef CONFIG_ASSABET_NEPONSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) printk( "Warning: Neponset detected but full support "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) "hasn't been configured in the kernel\n" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) platform_device_register_simple("neponset", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) neponset_resources, ARRAY_SIZE(neponset_resources));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) gpiod_add_lookup_table(&assabet_uart1_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) gpiod_add_lookup_table(&assabet_uart3_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) gpiod_add_lookup_table(&assabet_cf_vcc_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) sa11x0_register_fixed_regulator(0, &assabet_cf_vcc_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) assabet_cf_vcc_consumers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ARRAY_SIZE(assabet_cf_vcc_consumers),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) platform_device_register_resndata(NULL, "gpio-keys", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) &assabet_keys_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) sizeof(assabet_keys_pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) gpio_led_register_device(-1, &assabet_leds_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #ifndef ASSABET_PAL_VIDEO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) sa11x0_register_lcd(&lq039q2ds54_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) sa11x0_register_lcd(&pal_video);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ARRAY_SIZE(assabet_flash_resources));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) sa11x0_register_irda(&assabet_irda_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) sa11x0_register_mcp(&assabet_mcp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!machine_has_neponset())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) sa11x0_register_pcmcia(1, &assabet_cf_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * On Assabet, we must probe for the Neponset board _before_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * paging_init() has occurred to actually determine the amount
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * of RAM available. To do so, we map the appropriate IO section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * in the page table here in order to access GPIO registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static void __init map_sa1100_gpio_regs( void )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) unsigned long phys = __PREG(GPLR) & PMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) unsigned long virt = (unsigned long)io_p2v(phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) pmd_t *pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) pmd = pmd_off_k(virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) *pmd = __pmd(phys | prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) flush_pmd_entry(pmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * Read System Configuration "Register"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * (taken from "Intel StrongARM SA-1110 Microprocessor Development Board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * User's Guide", section 4.4.1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * This same scan is performed in arch/arm/boot/compressed/head-sa1100.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * to set up the serial port for decompression status messages. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * repeat it here because the kernel may not be loaded as a zImage, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * also because it's a hassle to communicate the SCR value to the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * from the decompressor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * Note that IRQs are guaranteed to be disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static void __init get_assabet_scr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) unsigned long scr, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) GPSR = 0x3fc; /* Write 0xFF to GPIO 9:2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) GPDR &= ~(0x3fc); /* Configure GPIO 9:2 as inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) for(i = 100; i--; ) /* Read GPIO 9:2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) scr = GPLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) GPDR |= 0x3fc; /* restore correct pin direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) scr &= 0x3fc; /* save as system configuration byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) SCR_value = scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) fixup_assabet(struct tag *tags, char **cmdline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* This must be done before any call to machine_has_neponset() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) map_sa1100_gpio_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) get_assabet_scr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (machine_has_neponset())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) printk("Neponset expansion board detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static void assabet_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (port->mapbase == _Ser1UTCR0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ASSABET_BCR_clear(ASSABET_BCR_RS232EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ASSABET_BCR_set(ASSABET_BCR_RS232EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static struct sa1100_port_fns assabet_port_fns __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .pm = assabet_uart_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static struct map_desc assabet_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) { /* Board Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .virtual = 0xf1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .pfn = __phys_to_pfn(0x12000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .length = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }, { /* MQ200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .virtual = 0xf2800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .pfn = __phys_to_pfn(0x4b800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .length = 0x00800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static void __init assabet_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) sa1100_map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) iotable_init(assabet_io_desc, ARRAY_SIZE(assabet_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * Set SUS bit in SDCR0 so serial port 1 functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * Its called GPCLKR0 in my SA1110 manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) Ser1SDCR0 |= SDCR0_SUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) MSC1 = (MSC1 & ~0xffff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) MSC_NonBrst | MSC_32BitStMem |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) MSC_RdAcc(2) | MSC_WrAcc(2) | MSC_Rec(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (!machine_has_neponset())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) sa1100_register_uart_fns(&assabet_port_fns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * When Neponset is attached, the first UART should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * UART3. That's what Angel is doing and many documents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * are stating this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * We do the Neponset mapping even if Neponset support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * isn't compiled in so the user will still get something on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * the expected physical serial port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * We no longer do this; not all boot loaders support it,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * and UART3 appears to be somewhat unreliable with blob.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) sa1100_register_uart(0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) sa1100_register_uart(2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) void __init assabet_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) unsigned int assabet_gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u32 def_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) sa1100_init_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (machine_has_neponset())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) def_val = ASSABET_BCR_DB1111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) def_val = ASSABET_BCR_DB1110;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * Angel sets this, but other bootloaders may not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * This must precede any driver calls to BCR_set() or BCR_clear().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) assabet_gpio_base = assabet_init_gpio((void *)&ASSABET_BCR, def_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) assabet_leds[0].gpio = assabet_gpio_base + 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) assabet_leds[1].gpio = assabet_gpio_base + 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) MACHINE_START(ASSABET, "Intel-Assabet")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .fixup = fixup_assabet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .map_io = assabet_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .nr_irqs = SA1100_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .init_irq = assabet_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .init_time = sa1100_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .init_machine = assabet_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .init_late = sa11x0_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #ifdef CONFIG_SA1111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .dma_zone_size = SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .restart = sa11x0_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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