Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *		http://www.samsung.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * S5PV210 - Clock register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef __ASM_ARCH_REGS_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define __ASM_ARCH_REGS_CLOCK_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define S3C_ADDR_BASE		0xF6000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define S3C_ADDR(x)		((void __iomem __force *)S3C_ADDR_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define S3C_VA_SYS		S3C_ADDR(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define S5P_CLKREG(x)		(S3C_VA_SYS + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define S5P_APLL_LOCK		S5P_CLKREG(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define S5P_MPLL_LOCK		S5P_CLKREG(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define S5P_EPLL_LOCK		S5P_CLKREG(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define S5P_VPLL_LOCK		S5P_CLKREG(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define S5P_APLL_CON		S5P_CLKREG(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define S5P_MPLL_CON		S5P_CLKREG(0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define S5P_EPLL_CON		S5P_CLKREG(0x110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define S5P_EPLL_CON1		S5P_CLKREG(0x114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define S5P_VPLL_CON		S5P_CLKREG(0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define S5P_CLK_SRC0		S5P_CLKREG(0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define S5P_CLK_SRC1		S5P_CLKREG(0x204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define S5P_CLK_SRC2		S5P_CLKREG(0x208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define S5P_CLK_SRC3		S5P_CLKREG(0x20C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define S5P_CLK_SRC4		S5P_CLKREG(0x210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define S5P_CLK_SRC5		S5P_CLKREG(0x214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define S5P_CLK_SRC6		S5P_CLKREG(0x218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define S5P_CLK_SRC_MASK0	S5P_CLKREG(0x280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define S5P_CLK_SRC_MASK1	S5P_CLKREG(0x284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define S5P_CLK_DIV0		S5P_CLKREG(0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define S5P_CLK_DIV1		S5P_CLKREG(0x304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define S5P_CLK_DIV2		S5P_CLKREG(0x308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define S5P_CLK_DIV3		S5P_CLKREG(0x30C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define S5P_CLK_DIV4		S5P_CLKREG(0x310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define S5P_CLK_DIV5		S5P_CLKREG(0x314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define S5P_CLK_DIV6		S5P_CLKREG(0x318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define S5P_CLK_DIV7		S5P_CLKREG(0x31C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define S5P_CLKGATE_MAIN0	S5P_CLKREG(0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define S5P_CLKGATE_MAIN1	S5P_CLKREG(0x404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define S5P_CLKGATE_MAIN2	S5P_CLKREG(0x408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define S5P_CLKGATE_PERI0	S5P_CLKREG(0x420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define S5P_CLKGATE_PERI1	S5P_CLKREG(0x424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define S5P_CLKGATE_SCLK0	S5P_CLKREG(0x440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define S5P_CLKGATE_SCLK1	S5P_CLKREG(0x444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define S5P_CLKGATE_IP0		S5P_CLKREG(0x460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define S5P_CLKGATE_IP1		S5P_CLKREG(0x464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define S5P_CLKGATE_IP2		S5P_CLKREG(0x468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define S5P_CLKGATE_IP3		S5P_CLKREG(0x46C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define S5P_CLKGATE_IP4		S5P_CLKREG(0x470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define S5P_CLKGATE_BLOCK	S5P_CLKREG(0x480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define S5P_CLKGATE_BUS0	S5P_CLKREG(0x484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define S5P_CLKGATE_BUS1	S5P_CLKREG(0x488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define S5P_CLK_OUT		S5P_CLKREG(0x500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* DIV/MUX STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define S5P_CLKDIV_STAT0	S5P_CLKREG(0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define S5P_CLKDIV_STAT1	S5P_CLKREG(0x1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define S5P_CLKMUX_STAT0	S5P_CLKREG(0x1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define S5P_CLKMUX_STAT1	S5P_CLKREG(0x1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* CLKSRC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define S5P_CLKSRC0_MUX200_SHIFT	(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define S5P_CLKSRC0_MUX200_MASK		(0x1 << S5P_CLKSRC0_MUX200_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define S5P_CLKSRC0_MUX166_MASK		(0x1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define S5P_CLKSRC0_MUX133_MASK		(0x1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* CLKSRC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define S5P_CLKSRC2_G3D_SHIFT           (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define S5P_CLKSRC2_G3D_MASK            (0x3 << S5P_CLKSRC2_G3D_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define S5P_CLKSRC2_MFC_SHIFT           (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define S5P_CLKSRC2_MFC_MASK            (0x3 << S5P_CLKSRC2_MFC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* CLKSRC6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define S5P_CLKSRC6_ONEDRAM_SHIFT       (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define S5P_CLKSRC6_ONEDRAM_MASK        (0x3 << S5P_CLKSRC6_ONEDRAM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* CLKDIV0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define S5P_CLKDIV0_APLL_SHIFT		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define S5P_CLKDIV0_APLL_MASK		(0x7 << S5P_CLKDIV0_APLL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define S5P_CLKDIV0_A2M_SHIFT		(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define S5P_CLKDIV0_A2M_MASK		(0x7 << S5P_CLKDIV0_A2M_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define S5P_CLKDIV0_HCLK200_SHIFT	(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define S5P_CLKDIV0_HCLK200_MASK	(0x7 << S5P_CLKDIV0_HCLK200_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define S5P_CLKDIV0_PCLK100_SHIFT	(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define S5P_CLKDIV0_PCLK100_MASK	(0x7 << S5P_CLKDIV0_PCLK100_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define S5P_CLKDIV0_HCLK166_SHIFT	(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define S5P_CLKDIV0_HCLK166_MASK	(0xF << S5P_CLKDIV0_HCLK166_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define S5P_CLKDIV0_PCLK83_SHIFT	(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define S5P_CLKDIV0_PCLK83_MASK		(0x7 << S5P_CLKDIV0_PCLK83_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define S5P_CLKDIV0_HCLK133_SHIFT	(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define S5P_CLKDIV0_HCLK133_MASK	(0xF << S5P_CLKDIV0_HCLK133_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define S5P_CLKDIV0_PCLK66_SHIFT	(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define S5P_CLKDIV0_PCLK66_MASK		(0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* CLKDIV2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define S5P_CLKDIV2_G3D_SHIFT           (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define S5P_CLKDIV2_G3D_MASK            (0xF << S5P_CLKDIV2_G3D_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define S5P_CLKDIV2_MFC_SHIFT           (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define S5P_CLKDIV2_MFC_MASK            (0xF << S5P_CLKDIV2_MFC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* CLKDIV6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define S5P_CLKDIV6_ONEDRAM_SHIFT       (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define S5P_CLKDIV6_ONEDRAM_MASK        (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define S5P_SWRESET		S5P_CLKREG(0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define S5P_ARM_MCS_CON		S5P_CLKREG(0x6100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Registers related to power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define S5P_PWR_CFG		S5P_CLKREG(0xC000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define S5P_EINT_WAKEUP_MASK	S5P_CLKREG(0xC004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define S5P_WAKEUP_MASK		S5P_CLKREG(0xC008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define S5P_PWR_MODE		S5P_CLKREG(0xC00C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define S5P_NORMAL_CFG		S5P_CLKREG(0xC010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define S5P_IDLE_CFG		S5P_CLKREG(0xC020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define S5P_STOP_CFG		S5P_CLKREG(0xC030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define S5P_STOP_MEM_CFG	S5P_CLKREG(0xC034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define S5P_SLEEP_CFG		S5P_CLKREG(0xC040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define S5P_OSC_FREQ		S5P_CLKREG(0xC100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define S5P_OSC_STABLE		S5P_CLKREG(0xC104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define S5P_PWR_STABLE		S5P_CLKREG(0xC108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define S5P_MTC_STABLE		S5P_CLKREG(0xC110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define S5P_CLAMP_STABLE	S5P_CLKREG(0xC114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define S5P_WAKEUP_STAT		S5P_CLKREG(0xC200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define S5P_BLK_PWR_STAT	S5P_CLKREG(0xC204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define S5P_OTHERS		S5P_CLKREG(0xE000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define S5P_OM_STAT		S5P_CLKREG(0xE100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define S5P_HDMI_PHY_CONTROL	S5P_CLKREG(0xE804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define S5P_USB_PHY_CONTROL	S5P_CLKREG(0xE80C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define S5P_DAC_PHY_CONTROL	S5P_CLKREG(0xE810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define S5P_INFORM0		S5P_CLKREG(0xF000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define S5P_INFORM1		S5P_CLKREG(0xF004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define S5P_INFORM2		S5P_CLKREG(0xF008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define S5P_INFORM3		S5P_CLKREG(0xF00C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define S5P_INFORM4		S5P_CLKREG(0xF010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define S5P_INFORM5		S5P_CLKREG(0xF014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define S5P_INFORM6		S5P_CLKREG(0xF018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define S5P_INFORM7		S5P_CLKREG(0xF01C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define S5P_RST_STAT		S5P_CLKREG(0xA000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define S5P_OSC_CON		S5P_CLKREG(0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define S5P_MDNIE_SEL		S5P_CLKREG(0x7008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define S5P_MIPI_PHY_CON0	S5P_CLKREG(0x7200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define S5P_MIPI_PHY_CON1	S5P_CLKREG(0x7204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define S5P_IDLE_CFG_TL_MASK	(3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define S5P_IDLE_CFG_TM_MASK	(3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define S5P_IDLE_CFG_TL_ON	(2 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define S5P_IDLE_CFG_TM_ON	(2 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define S5P_IDLE_CFG_DIDLE	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define S5P_CFG_WFI_CLEAN		(~(3 << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define S5P_CFG_WFI_IDLE		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define S5P_CFG_WFI_STOP		(2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define S5P_CFG_WFI_SLEEP		(3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define S5P_OTHER_SYS_INT		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define S5P_OTHER_STA_TYPE		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define S5P_OTHER_SYSC_INTOFF		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define STA_TYPE_EXPON			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define STA_TYPE_SFR			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define S5P_PWR_STA_EXP_SCALE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define S5P_PWR_STA_CNT			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define S5P_PWR_STABLE_COUNT		85500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define S5P_SLEEP_CFG_OSC_EN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define S5P_SLEEP_CFG_USBOSC_EN		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* OTHERS Resgister */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define S5P_OTHERS_USB_SIG_MASK		(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* S5P_DAC_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define S5P_DAC_ENABLE			(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define S5P_DAC_DISABLE			(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif /* __ASM_ARCH_REGS_CLOCK_H */