^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2003 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * VR1000 - CPLD control constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Machine VR1000 - IRQ Number definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Machine VR1000 - Memory map definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __MACH_S3C24XX_VR1000_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __MACH_S3C24XX_VR1000_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* irq numbers to onboard peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define VR1000_IRQ_USBOC IRQ_EINT19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define VR1000_IRQ_IDE0 IRQ_EINT16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define VR1000_IRQ_IDE1 IRQ_EINT17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define VR1000_IRQ_SERIAL IRQ_EINT12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VR1000_IRQ_DM9000A IRQ_EINT10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VR1000_IRQ_DM9000N IRQ_EINT9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VR1000_IRQ_SMALERT IRQ_EINT8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* we put the CPLD registers next, to get them out of the way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* next, we have the PC104 ISA interrupt registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 0xE0000000 contains the IO space that is split by speed and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * whether the access is for 8 or 16bit IO... this ensures that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * the correct access is made
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 0x10000000 of space, partitioned as so:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * 0x00000000 to 0x04000000 8bit, slow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * 0x04000000 to 0x08000000 16bit, slow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * 0x08000000 to 0x0C000000 16bit, net
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 0x0C000000 to 0x10000000 16bit, fast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * each of these spaces has the following in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * 0x02000000 to 0x02100000 1MB IDE primary channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * 0x02100000 to 0x02200000 1MB IDE primary channel aux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * 0x02200000 to 0x02400000 1MB IDE secondary channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * 0x02600000 to 0x02700000 1MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * the phyiscal layout of the zones are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * nGCS2 - 8bit, slow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * nGCS3 - 16bit, slow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * nGCS4 - 16bit, net
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * nGCS5 - 16bit, fast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define VR1000_VA_MULTISPACE (0xE0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* physical offset addresses for the peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define VR1000_PA_IDEPRI (0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define VR1000_PA_IDEPRIAUX (0x02800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define VR1000_PA_IDESEC (0x03000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define VR1000_PA_IDESECAUX (0x03800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define VR1000_PA_DM9000 (0x05000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define VR1000_PA_SERIAL (0x11800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* VR1000 ram is in CS1, with A26..A24 = 2_101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* some configurations for the peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define VR1000_DM9000_CS VR1000_VAM_CS4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #endif /* __MACH_S3C24XX_VR1000_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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