Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* linux/arch/arm/plat-s3c64xx/sleep.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright 2008 Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *	http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * S3C64XX CPU sleep code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #undef S3C64XX_VA_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S3C64XX_VA_GPIO (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	/* Sleep magic, the word before the resume entry point so that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	 * bootloader can check for a resumeable image. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	.word	0x2bedf00d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	/* s3c_cpu_reusme
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	 * This is the entry point, stored by whatever method the bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	 * requires to get the kernel runnign again. This code expects to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	 * entered with no caches live and the MMU disabled. It will then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	 * restore the MMU and other basic CP registers saved and restart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	 * the kernel C code to finish the resume code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ENTRY(s3c_cpu_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	msr	cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	ldr	r2, =LL_UART		/* for debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S3C64XX_GPNCON			(S3C64XX_GPN_BASE + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C64XX_GPNDAT			(S3C64XX_GPN_BASE + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S3C64XX_GPN_CONMASK(__gpio)	(0x3 << ((__gpio) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S3C64XX_GPN_OUTPUT(__gpio)	(0x1 << ((__gpio) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	/* Initialise the GPIO state if we are debugging via the SMDK LEDs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	 * as the uboot version supplied resets these to inputs during the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	 * resume checks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	ldr	r3, =S3C64XX_PA_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	ldr	r0, [ r3, #S3C64XX_GPNCON ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	bic	r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			  S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	orr	r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 			  S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	str	r0, [ r3, #S3C64XX_GPNCON ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	ldr	r0, [ r3, #S3C64XX_GPNDAT ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	bic	r0, r0, #0xf << 12			@ GPN12..15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	orr	r0, r0, #1 << 15			@ GPN15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	str	r0, [ r3, #S3C64XX_GPNDAT ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	b	cpu_resume