Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2004 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * S3C2410 Power Manager (Suspend-To-RAM) support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Based on PXA/SA1100 sleep code by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *	Nicolas Pitre, (c) 2002 Monta Vista Software Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *	Cliff Brake, (c) 2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/serial_s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "regs-clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * S3C24XX_DEBUG_RESUME is dangerous if your bootloader does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * reset the UART configuration, only enable if you really need this!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) //#define S3C24XX_DEBUG_RESUME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	/* sleep magic, to allow the bootloader to check for an valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	 * image to resume to. Must be the first word before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	 * s3c_cpu_resume entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	.word	0x2bedf00d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	/* s3c_cpu_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	 * resume code entry for bootloader to call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ENTRY(s3c_cpu_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	mov	r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	msr	cpsr_c, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	@@ load UART to allow us to print the two characters for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	@@ resume debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	mov	r2, #S3C24XX_PA_UART & 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	orr	r2, r2, #S3C24XX_PA_UART & 0xff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	/* SMDK2440 LED set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	mov	r14, #S3C24XX_PA_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	ldr	r12, [ r14, #0x54 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	bic	r12, r12, #3<<4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	orr	r12, r12, #1<<7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	str	r12, [ r14, #0x54 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #ifdef S3C24XX_DEBUG_RESUME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	mov	r3, #'L'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	strb	r3, [ r2, #S3C2410_UTXH ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 1001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	ldrb	r14, [ r3, #S3C2410_UTRSTAT ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	tst	r14, #S3C2410_UTRSTAT_TXE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	beq	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif /* S3C24XX_DEBUG_RESUME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	b	cpu_resume