^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2007 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * S3C2412 Power Manager low-level sleep support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "regs-irq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .global s3c2412_sleep_enter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) s3c2412_sleep_enter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) mov r0, #0 /* argument for coprocessors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ldr r1, =S3C2410_INTPND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ldr r2, =S3C2410_SRCPND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ldr r3, =S3C2410_EINTPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) teq r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) bl s3c2412_sleep_enter1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) teq pc, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) bl s3c2412_sleep_enter1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* this is called twice, first with the Z flag to ensure that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * instructions have been loaded into the cache, and the second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * time to try and suspend the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) s3c2412_sleep_enter1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) mcr p15, 0, r0, c7, c10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) mcrne p15, 0, r0, c7, c0, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* if we return from here, it is because an interrupt was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * active when we tried to shutdown. Try and ack the IRQ and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * retry, as simply returning causes the system to lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ldrne r9, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) strne r9, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ldrne r9, [r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) strne r9, [r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ldrne r9, [r3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) strne r9, [r3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) bne s3c2412_sleep_enter1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ret lr