Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2004 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * S3C2410 Power Manager (Suspend-To-RAM) support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Based on PXA/SA1100 sleep code by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *	Nicolas Pitre, (c) 2002 Monta Vista Software Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *	Cliff Brake, (c) 2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/serial_s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "regs-clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "regs-mem-s3c24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	/* s3c2410_cpu_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	 * put the cpu into sleep mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ENTRY(s3c2410_cpu_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	@@ prepare cpu to sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	ldr	r4, =S3C2410_REFRESH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	ldr	r5, =S3C24XX_MISCCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	ldr	r6, =S3C2410_CLKCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	ldr	r7, [r4]		@ get REFRESH (and ensure in TLB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	ldr	r8, [r5]		@ get MISCCR (and ensure in TLB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	ldr	r9, [r6]		@ get CLKCON (and ensure in TLB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	orr	r7, r7, #S3C2410_REFRESH_SELF	@ SDRAM sleep command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	orr	r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	orr	r9, r9, #S3C2410_CLKCON_POWER	@ power down command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	teq	pc, #0			@ first as a trial-run to load cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	bl	s3c2410_do_sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	teq	r0, r0			@ now do it for real
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	b	s3c2410_do_sleep	@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	@@ align next bit of code to cache line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) s3c2410_do_sleep:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	streq	r7, [r4]			@ SDRAM sleep command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	streq	r8, [r5]			@ SDRAM power-down config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	streq	r9, [r6]			@ CPU sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 1:	beq	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	ret	lr