Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) // Copyright (c) 2010 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) //		http://www.samsung.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) // S3C64XX setup information for IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_data/ata-samsung_cf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "regs-clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "gpio-cfg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "gpio-samsung.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) void s3c64xx_ide_setup_gpio(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	/* Independent CF interface, CF chip select configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	writel(reg | MEM_SYS_CFG_INDEP_CF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	/* Set XhiDATA[15:0] pins as CF Data[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	/* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	/* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }