Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) // Copyright 2009 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) //	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) //	http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * NOTE: Code in this file is not used when booting with Device Tree support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/serial_s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "regs-clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "devs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "sdhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "iic-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "s3c64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "onenand-core-s3c64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void __init s3c6400_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	/* setup SDHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	s3c6400_default_sdhci0();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	s3c6400_default_sdhci1();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	s3c6400_default_sdhci2();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	/* the i2c devices are directly compatible with s3c2440 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	s3c_i2c0_setname("s3c2440-i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	s3c_device_nand.name = "s3c6400-nand";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	s3c_onenand_setname("s3c6400-onenand");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	s3c64xx_onenand1_setname("s3c6400-onenand");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void __init s3c6400_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	/* VIC0 does not have IRQS 5..7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	 * VIC1 is fully populated. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	s3c64xx_init_irq(~0 & ~(0xf << 5), ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct bus_type s3c6400_subsys = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	.name		= "s3c6400-core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	.dev_name	= "s3c6400-core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static struct device s3c6400_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	.bus	= &s3c6400_subsys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int __init s3c6400_core_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	/* Not applicable when using DT. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	if (of_have_populated_dt() || soc_is_s3c64xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	return subsys_system_register(&s3c6400_subsys, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) core_initcall(s3c6400_core_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int __init s3c6400_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	printk("S3C6400: Initialising architecture\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 	return device_register(&s3c6400_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }