^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2004-2005 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // http://www.simtec.co.uk/products/SWLINUX/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Common code for S3C24XX machines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/serial_s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <clocksource/samsung_pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_data/clk-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_data/dma-s3c24xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/clk/samsung.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "hardware-s3c24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "regs-clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/system_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/system_misc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "dma-s3c24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "devs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "pwm-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "s3c24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* table of supported CPUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const char name_s3c2410[] = "S3C2410";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const char name_s3c2412[] = "S3C2412";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const char name_s3c2416[] = "S3C2416/S3C2450";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const char name_s3c2440[] = "S3C2440";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const char name_s3c2442[] = "S3C2442";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const char name_s3c2442b[] = "S3C2442B";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const char name_s3c2443[] = "S3C2443";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const char name_s3c2410a[] = "S3C2410A";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const char name_s3c2440a[] = "S3C2440A";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct cpu_table cpu_ids[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .idcode = 0x32410000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .idmask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .map_io = s3c2410_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .init_uarts = s3c2410_init_uarts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .init = s3c2410_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .name = name_s3c2410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .idcode = 0x32410002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .idmask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .map_io = s3c2410_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .init_uarts = s3c2410_init_uarts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .init = s3c2410a_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .name = name_s3c2410a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .idcode = 0x32440000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .idmask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .map_io = s3c2440_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .init_uarts = s3c244x_init_uarts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .init = s3c2440_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .name = name_s3c2440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .idcode = 0x32440001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .idmask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .map_io = s3c2440_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .init_uarts = s3c244x_init_uarts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .init = s3c2440_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .name = name_s3c2440a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .idcode = 0x32440aaa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .idmask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .map_io = s3c2442_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .init_uarts = s3c244x_init_uarts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .init = s3c2442_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .name = name_s3c2442
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .idcode = 0x32440aab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .idmask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .map_io = s3c2442_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .init_uarts = s3c244x_init_uarts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .init = s3c2442_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .name = name_s3c2442b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .idcode = 0x32412001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .idmask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .map_io = s3c2412_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .init_uarts = s3c2412_init_uarts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .init = s3c2412_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .name = name_s3c2412,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { /* a newer version of the s3c2412 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .idcode = 0x32412003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .idmask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .map_io = s3c2412_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .init_uarts = s3c2412_init_uarts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .init = s3c2412_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .name = name_s3c2412,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { /* a strange version of the s3c2416 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .idcode = 0x32450003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .idmask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .map_io = s3c2416_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .init_uarts = s3c2416_init_uarts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .init = s3c2416_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .name = name_s3c2416,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .idcode = 0x32443001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .idmask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .map_io = s3c2443_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .init_uarts = s3c2443_init_uarts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .init = s3c2443_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .name = name_s3c2443,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* minimal IO mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct map_desc s3c_iodesc[] __initdata __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) IODESC_ENT(GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) IODESC_ENT(IRQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) IODESC_ENT(MEMCTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) IODESC_ENT(UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* read cpu identificaiton code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static unsigned long s3c24xx_read_idcode_v5(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #if defined(CONFIG_CPU_S3C2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 gs = __raw_readl(S3C24XX_GSTATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* test for s3c2416 or similar device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if ((gs >> 16) == 0x3245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return gs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #if defined(CONFIG_CPU_S3C2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return __raw_readl(S3C2412_GSTATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 1UL; /* don't look like an 2400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static unsigned long s3c24xx_read_idcode_v4(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return __raw_readl(S3C2410_GSTATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void s3c24xx_default_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned long tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* idle the system by using the idle mode which will wait for an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * interrupt to happen before restarting the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Warning: going into idle state upsets jtag scanning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) S3C2410_CLKCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* the samsung port seems to do a loop and then unset idle.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) for (i = 0; i < 50; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* this bit is not cleared on re-start... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) S3C2410_CLKCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static struct samsung_pwm_variant s3c24xx_pwm_variant = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .div_base = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .has_tint_cstat = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .tclk_mask = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) arm_pm_idle = s3c24xx_default_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* initialise the io descriptors we need for initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) iotable_init(mach_desc, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (cpu_architecture() >= CPU_ARCH_ARMv5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) samsung_cpu_id = s3c24xx_read_idcode_v5();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) samsung_cpu_id = s3c24xx_read_idcode_v4();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) void __init s3c24xx_set_timer_source(unsigned int event, unsigned int source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) void __init s3c24xx_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) samsung_pwm_clocksource_init(S3C_VA_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) timer_irqs, &s3c24xx_pwm_variant);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Serial port registrations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define S3C2410_PA_UART0 (S3C24XX_PA_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct resource s3c2410_uart0_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) NULL, IORESOURCE_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static struct resource s3c2410_uart1_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) NULL, IORESOURCE_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static struct resource s3c2410_uart2_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) NULL, IORESOURCE_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static struct resource s3c2410_uart3_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) NULL, IORESOURCE_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .resources = s3c2410_uart0_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .resources = s3c2410_uart1_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .resources = s3c2410_uart2_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .resources = s3c2410_uart3_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define s3c24xx_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) }))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct resource s3c2410_dma_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [1] = DEFINE_RES_IRQ(IRQ_DMA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) [2] = DEFINE_RES_IRQ(IRQ_DMA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [3] = DEFINE_RES_IRQ(IRQ_DMA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [4] = DEFINE_RES_IRQ(IRQ_DMA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) S3C24XX_DMA_CHANREQ(2, 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) S3C24XX_DMA_CHANREQ(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) S3C24XX_DMA_CHANREQ(3, 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) S3C24XX_DMA_CHANREQ(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) S3C24XX_DMA_CHANREQ(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct dma_slave_map s3c2410_dma_slave_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { "s3c2410-sdi", "rx-tx", (void *)DMACH_SDI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { "s3c2410-spi.0", "rx", (void *)DMACH_SPI0_RX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { "s3c2410-spi.0", "tx", (void *)DMACH_SPI0_TX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { "s3c2410-spi.1", "rx", (void *)DMACH_SPI1_RX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { "s3c2410-spi.1", "tx", (void *)DMACH_SPI1_TX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * The DMA request source[1] (DMACH_UARTx_SRC2) are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * not used in the UART driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { "s3c2410-uart.0", "rx", (void *)DMACH_UART0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { "s3c2410-uart.0", "tx", (void *)DMACH_UART0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { "s3c2410-uart.1", "rx", (void *)DMACH_UART1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { "s3c2410-uart.1", "tx", (void *)DMACH_UART1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { "s3c2410-uart.2", "rx", (void *)DMACH_UART2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { "s3c2410-uart.2", "tx", (void *)DMACH_UART2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static struct s3c24xx_dma_platdata s3c2410_dma_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .num_phy_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .channels = s3c2410_dma_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .num_channels = DMACH_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .slave_map = s3c2410_dma_slave_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .slavecnt = ARRAY_SIZE(s3c2410_dma_slave_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct platform_device s3c2410_device_dma = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .name = "s3c2410-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .num_resources = ARRAY_SIZE(s3c2410_dma_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .resource = s3c2410_dma_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .dma_mask = &s3c24xx_device_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .platform_data = &s3c2410_dma_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #ifdef CONFIG_CPU_S3C2412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct dma_slave_map s3c2412_dma_slave_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { "s3c2412-sdi", "rx-tx", (void *)DMACH_SDI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { "s3c2412-spi.0", "rx", (void *)DMACH_SPI0_RX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { "s3c2412-spi.0", "tx", (void *)DMACH_SPI0_TX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { "s3c2412-spi.1", "rx", (void *)DMACH_SPI1_RX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { "s3c2412-spi.1", "tx", (void *)DMACH_SPI1_TX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { "s3c2412-iis", "rx", (void *)DMACH_I2S_IN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { "s3c2412-iis", "tx", (void *)DMACH_I2S_OUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct s3c24xx_dma_platdata s3c2412_dma_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .num_phy_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .channels = s3c2412_dma_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .num_channels = DMACH_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .slave_map = s3c2412_dma_slave_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .slavecnt = ARRAY_SIZE(s3c2412_dma_slave_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct platform_device s3c2412_device_dma = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .name = "s3c2412-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .num_resources = ARRAY_SIZE(s3c2410_dma_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .resource = s3c2410_dma_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .dma_mask = &s3c24xx_device_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .platform_data = &s3c2412_dma_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #if defined(CONFIG_CPU_S3C2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) S3C24XX_DMA_CHANREQ(6, 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) S3C24XX_DMA_CHANREQ(2, 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) S3C24XX_DMA_CHANREQ(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) S3C24XX_DMA_CHANREQ(3, 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) S3C24XX_DMA_CHANREQ(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) S3C24XX_DMA_CHANREQ(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) S3C24XX_DMA_CHANREQ(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) S3C24XX_DMA_CHANREQ(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) S3C24XX_DMA_CHANREQ(6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) S3C24XX_DMA_CHANREQ(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const struct dma_slave_map s3c2440_dma_slave_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* TODO: DMACH_XD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* TODO: DMACH_XD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { "s3c2410-spi.0", "rx", (void *)DMACH_SPI0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { "s3c2410-spi.0", "tx", (void *)DMACH_SPI0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { "s3c2410-spi.1", "rx", (void *)DMACH_SPI1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { "s3c2410-spi.1", "tx", (void *)DMACH_SPI1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { "s3c2440-uart.3", "rx", (void *)DMACH_UART3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { "s3c2440-uart.3", "tx", (void *)DMACH_UART3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* TODO: DMACH_TIMER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) { "samsung-ac97", "rx", (void *)DMACH_PCM_IN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) { "samsung-ac97", "tx", (void *)DMACH_PCM_OUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) { "samsung-ac97", "rx", (void *)DMACH_MIC_IN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static struct s3c24xx_dma_platdata s3c2440_dma_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .num_phy_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .channels = s3c2440_dma_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .num_channels = DMACH_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .slave_map = s3c2440_dma_slave_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .slavecnt = ARRAY_SIZE(s3c2440_dma_slave_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct platform_device s3c2440_device_dma = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .name = "s3c2410-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .num_resources = ARRAY_SIZE(s3c2410_dma_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .resource = s3c2410_dma_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .dma_mask = &s3c24xx_device_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .platform_data = &s3c2440_dma_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static struct resource s3c2443_dma_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const struct dma_slave_map s3c2443_dma_slave_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) { "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) { "s3c2443-spi.0", "rx", (void *)DMACH_SPI0_RX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) { "s3c2443-spi.0", "tx", (void *)DMACH_SPI0_TX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) { "s3c2443-spi.1", "rx", (void *)DMACH_SPI1_RX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { "s3c2443-spi.1", "tx", (void *)DMACH_SPI1_TX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) { "s3c2440-uart.3", "rx", (void *)DMACH_UART3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) { "s3c2440-uart.3", "tx", (void *)DMACH_UART3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static struct s3c24xx_dma_platdata s3c2443_dma_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .num_phy_channels = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .channels = s3c2443_dma_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .num_channels = DMACH_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .slave_map = s3c2443_dma_slave_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .slavecnt = ARRAY_SIZE(s3c2443_dma_slave_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct platform_device s3c2443_device_dma = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .name = "s3c2443-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .num_resources = ARRAY_SIZE(s3c2443_dma_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .resource = s3c2443_dma_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .dma_mask = &s3c24xx_device_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .platform_data = &s3c2443_dma_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) void __init s3c2410_init_clocks(int xtal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #ifdef CONFIG_CPU_S3C2412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) void __init s3c2412_init_clocks(int xtal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #ifdef CONFIG_CPU_S3C2416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) void __init s3c2416_init_clocks(int xtal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) void __init s3c2440_init_clocks(int xtal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) void __init s3c2442_init_clocks(int xtal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #ifdef CONFIG_CPU_S3C2443
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) void __init s3c2443_init_clocks(int xtal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) defined(CONFIG_CPU_S3C2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static struct resource s3c2410_dclk_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) [0] = DEFINE_RES_MEM(0x56000084, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static struct s3c2410_clk_platform_data s3c_clk_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .modify_misccr = s3c2410_modify_misccr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct platform_device s3c2410_device_dclk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .name = "s3c2410-dclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .num_resources = ARRAY_SIZE(s3c2410_dclk_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .resource = s3c2410_dclk_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .platform_data = &s3c_clk_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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