^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __ARCH_ARM_MACH_S3C24XX_S3C2412_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "map-s3c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S3C2412_REFRESH S3C2412_MEMREG(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_H */