^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2006 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // http://armlinux.simtec.co.uk/.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/serial_s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/proc-fns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/system_misc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "regs-clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "devs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "s3c24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "nand-core-s3c24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "regs-dsc-s3c24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "s3c2412-power.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifndef CONFIG_CPU_S3C2412_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static inline void s3c2412_init_gpio2(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define s3c2412_init_gpio2() do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Initial IO mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct map_desc s3c2412_iodesc[] __initdata __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) IODESC_ENT(CLKPWR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) IODESC_ENT(TIMER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) IODESC_ENT(WATCHDOG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .virtual = (unsigned long)S3C2412_VA_SSMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .pfn = __phys_to_pfn(S3C2412_PA_SSMC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .length = SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .virtual = (unsigned long)S3C2412_VA_EBI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .pfn = __phys_to_pfn(S3C2412_PA_EBI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .length = SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* uart registration process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* rename devices that are s3c2412/s3c2413 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) s3c_device_sdi.name = "s3c2412-sdi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) s3c_device_lcd.name = "s3c2412-lcd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) s3c_nand_setname("s3c2412-nand");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* alter IRQ of SDI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) s3c_device_sdi.resource[1].end = IRQ_S3C2412_SDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* spi channel related changes, s3c2412/13 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) s3c_device_spi0.name = "s3c2412-spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) s3c_device_spi1.name = "s3c2412-spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* s3c2412_idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * use the standard idle call by ensuring the idle mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * in power config, then issuing the idle co-processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void s3c2412_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* ensure our idle mode is to go to idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) tmp = __raw_readl(S3C2412_PWRCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __raw_writel(tmp, S3C2412_PWRCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* s3c2412_map_io
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * register the standard cpu IO areas, and any passed in from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * machine specific initialisation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void __init s3c2412_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* move base of IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) s3c2412_init_gpio2();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* set our idle function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) arm_pm_idle = s3c2412_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* register our io-tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* need to register the subsystem before we actually register the device, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * we also need to ensure that it has been initialised before any of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * drivers even try to use it (even if not on an s3c2412 based system)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * as a driver which may support both 2410 and 2440 may try and use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct bus_type s3c2412_subsys = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .name = "s3c2412-core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .dev_name = "s3c2412-core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int __init s3c2412_core_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return subsys_system_register(&s3c2412_subsys, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) core_initcall(s3c2412_core_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct device s3c2412_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .bus = &s3c2412_subsys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int __init s3c2412_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) printk("S3C2412: Initialising architecture\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) register_syscore_ops(&s3c2412_pm_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) register_syscore_ops(&s3c24xx_irq_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return device_register(&s3c2412_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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