Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *	http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define S3C24XX_PWRREG(x)			((x) + S3C24XX_VA_CLKPWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define S3C2412_PWRMODECON			S3C24XX_PWRREG(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define S3C2412_PWRCFG				S3C24XX_PWRREG(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define S3C2412_INFORM0				S3C24XX_PWRREG(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define S3C2412_INFORM1				S3C24XX_PWRREG(0x74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S3C2412_INFORM2				S3C24XX_PWRREG(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S3C2412_INFORM3				S3C24XX_PWRREG(0x7C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S3C2412_PWRCFG_BATF_IRQ			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S3C2412_PWRCFG_BATF_IGNORE		(2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S3C2412_PWRCFG_BATF_SLEEP		(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S3C2412_PWRCFG_BATF_MASK		(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S3C2412_PWRCFG_STANDBYWFI_IGNORE	(0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S3C2412_PWRCFG_STANDBYWFI_IDLE		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S3C2412_PWRCFG_STANDBYWFI_STOP		(2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S3C2412_PWRCFG_STANDBYWFI_SLEEP		(3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define S3C2412_PWRCFG_STANDBYWFI_MASK		(3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C2412_PWRCFG_RTC_MASKIRQ		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S3C2412_PWRCFG_NAND_NORST		(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H */