Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2008 Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *      http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *      Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * S3C - USB2.0 Highspeed/OtG device PHY registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Note, this is a separate header file as some of the clock framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * needs to touch this if the clk_48m is used as the USB OHCI or other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * peripheral source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* S3C64XX_PA_USB_HSPHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S3C_HSOTG_PHYREG(x)	((x) + S3C_VA_USB_HSPHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S3C_PHYPWR				S3C_HSOTG_PHYREG(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define S3C_PHYPWR_NORMAL_MASK			(0x19 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S3C_PHYPWR_OTG_DISABLE			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S3C_PHYPWR_ANALOG_POWERDOWN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SRC_PHYPWR_FORCE_SUSPEND		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define S3C_PHYCLK				S3C_HSOTG_PHYREG(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S3C_PHYCLK_MODE_USB11			(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C_PHYCLK_EXT_OSC			(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S3C_PHYCLK_CLK_FORCE			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C_PHYCLK_ID_PULL			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define S3C_PHYCLK_CLKSEL_MASK			(0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S3C_PHYCLK_CLKSEL_SHIFT			(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S3C_PHYCLK_CLKSEL_48M			(0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S3C_PHYCLK_CLKSEL_12M			(0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S3C_PHYCLK_CLKSEL_24M			(0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S3C_RSTCON				S3C_HSOTG_PHYREG(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S3C_RSTCON_PHYCLK			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S3C_RSTCON_HCLK				(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S3C_RSTCON_PHY				(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S3C_PHYTUNE				S3C_HSOTG_PHYREG(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */