^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2008 Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * S3C64XX - syscon power and sleep control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __MACH_S3C64XX_REGS_SYSCON_POWER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __MACH_S3C64XX_REGS_SYSCON_POWER_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define S3C64XX_PWR_CFG S3C_SYSREG(0x804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define S3C64XX_PWRCFG_OSC_OTG_DISABLE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S3C64XX_PWRCFG_MMC2_DISABLE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S3C64XX_PWRCFG_MMC1_DISABLE (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S3C64XX_PWRCFG_MMC0_DISABLE (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S3C64XX_PWRCFG_HSI_DISABLE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S3C64XX_PWRCFG_TS_DISABLE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S3C64XX_PWRCFG_RTC_TICK_DISABLE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S3C64XX_PWRCFG_RTC_ALARM_DISABLE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define S3C64XX_PWRCFG_MSM_DISABLE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S3C64XX_PWRCFG_KEY_DISABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S3C64XX_PWRCFG_BATF_DISABLE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S3C64XX_PWRCFG_CFG_WFI_MASK (0x3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define S3C64XX_PWRCFG_CFG_WFI_SHIFT (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S3C64XX_PWRCFG_CFG_WFI_IGNORE (0x0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C64XX_PWRCFG_CFG_WFI_IDLE (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S3C64XX_PWRCFG_CFG_WFI_STOP (0x2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C64XX_PWRCFG_CFG_WFI_SLEEP (0x3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S3C64XX_PWRCFG_CFG_BATFLT_MASK (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE (0x0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S3C64XX_PWRCFG_CFG_BATFLT_IRQ (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S3C64XX_PWRCFG_CFG_BAT_WAKE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S3C64XX_PWRCFG_OSC27_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S3C64XX_EINT_MASK S3C_SYSREG(0x808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C64XX_NORMAL_CFG S3C_SYSREG(0x810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S3C64XX_NORMALCFG_IROM_ON (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S3C64XX_NORMALCFG_DOMAIN_ETM_ON (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S3C64XX_NORMALCFG_DOMAIN_S_ON (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define S3C64XX_NORMALCFG_DOMAIN_F_ON (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define S3C64XX_NORMALCFG_DOMAIN_P_ON (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define S3C64XX_NORMALCFG_DOMAIN_I_ON (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define S3C64XX_NORMALCFG_DOMAIN_G_ON (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define S3C64XX_NORMALCFG_DOMAIN_V_ON (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define S3C64XX_STOP_CFG S3C_SYSREG(0x814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define S3C64XX_STOPCFG_MEMORY_ARM_ON (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S3C64XX_STOPCFG_TOP_MEMORY_ON (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define S3C64XX_STOPCFG_ARM_LOGIC_ON (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define S3C64XX_STOPCFG_TOP_LOGIC_ON (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S3C64XX_STOPCFG_OSC_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define S3C64XX_SLEEP_CFG S3C_SYSREG(0x818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define S3C64XX_SLEEPCFG_OSC_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define S3C64XX_STOP_MEM_CFG S3C_SYSREG(0x81c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define S3C64XX_STOPMEMCFG_OTG_RETAIN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define S3C64XX_STOPMEMCFG_HSMCC_RETAIN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define S3C64XX_STOPMEMCFG_IROM_RETAIN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define S3C64XX_STOPMEMCFG_IRDA_RETAIN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define S3C64XX_STOPMEMCFG_NFCON_RETAIN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define S3C64XX_OSC_STABLE S3C_SYSREG(0x824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define S3C64XX_PWR_STABLE S3C_SYSREG(0x828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define S3C64XX_WAKEUP_STAT S3C_SYSREG(0x908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define S3C64XX_WAKEUPSTAT_MMC2 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define S3C64XX_WAKEUPSTAT_MMC1 (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define S3C64XX_WAKEUPSTAT_MMC0 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define S3C64XX_WAKEUPSTAT_HSI (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define S3C64XX_WAKEUPSTAT_BATFLT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define S3C64XX_WAKEUPSTAT_MSM (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define S3C64XX_WAKEUPSTAT_KEY (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define S3C64XX_WAKEUPSTAT_TS (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define S3C64XX_WAKEUPSTAT_RTC_TICK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define S3C64XX_WAKEUPSTAT_RTC_ALARM (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define S3C64XX_WAKEUPSTAT_EINT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define S3C64XX_BLK_PWR_STAT S3C_SYSREG(0x90c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define S3C64XX_BLKPWRSTAT_G (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define S3C64XX_BLKPWRSTAT_ETM (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define S3C64XX_BLKPWRSTAT_S (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define S3C64XX_BLKPWRSTAT_F (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define S3C64XX_BLKPWRSTAT_P (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define S3C64XX_BLKPWRSTAT_I (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define S3C64XX_BLKPWRSTAT_V (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define S3C64XX_BLKPWRSTAT_TOP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define S3C64XX_INFORM0 S3C_SYSREG(0xA00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define S3C64XX_INFORM1 S3C_SYSREG(0xA04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define S3C64XX_INFORM2 S3C_SYSREG(0xA08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define S3C64XX_INFORM3 S3C_SYSREG(0xA0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif /* __MACH_S3C64XX_REGS_SYSCON_POWER_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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