Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2009 Andy Green <andy@warmcat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * S3C64XX SROM definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __MACH_S3C64XX_REGS_SROM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __MACH_S3C64XX_REGS_SROM_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define S3C64XX_SROMREG(x)	(S3C_VA_MEM + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define S3C64XX_SROM_BW		S3C64XX_SROMREG(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define S3C64XX_SROM_BC0	S3C64XX_SROMREG(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define S3C64XX_SROM_BC1	S3C64XX_SROMREG(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define S3C64XX_SROM_BC2	S3C64XX_SROMREG(0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S3C64XX_SROM_BC3	S3C64XX_SROMREG(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S3C64XX_SROM_BC4	S3C64XX_SROMREG(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S3C64XX_SROM_BC5	S3C64XX_SROMREG(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S3C64XX_SROM_BW__DATAWIDTH__SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S3C64XX_SROM_BW__WAITENABLE__SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S3C64XX_SROM_BW__BYTEENABLE__SHIFT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S3C64XX_SROM_BW__CS_MASK		0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S3C64XX_SROM_BW__NCS0__SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C64XX_SROM_BW__NCS1__SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S3C64XX_SROM_BW__NCS2__SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C64XX_SROM_BW__NCS3__SHIFT	0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define S3C64XX_SROM_BW__NCS4__SHIFT	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * applies to same to BCS0 - BCS4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S3C64XX_SROM_BCX__PMC__SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S3C64XX_SROM_BCX__PMC__MASK	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S3C64XX_SROM_BCX__TACP__SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S3C64XX_SROM_BCX__TACP__MASK	0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S3C64XX_SROM_BCX__TCAH__SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S3C64XX_SROM_BCX__TCAH__MASK	0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C64XX_SROM_BCX__TCOH__SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S3C64XX_SROM_BCX__TCOH__MASK	0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S3C64XX_SROM_BCX__TACC__SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S3C64XX_SROM_BCX__TACC__MASK	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S3C64XX_SROM_BCX__TCOS__SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define S3C64XX_SROM_BCX__TCOS__MASK	0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define S3C64XX_SROM_BCX__TACS__SHIFT	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define S3C64XX_SROM_BCX__TACS__MASK	0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #endif /* __MACH_S3C64XX_REGS_SROM_H */