^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2007 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * S3C2443 clock register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __ASM_ARM_REGS_S3C2443_CLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __ASM_ARM_REGS_S3C2443_CLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "map-s3c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S3C2443_PLLCON_MDIVSHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S3C2443_PLLCON_PDIVSHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S3C2443_PLLCON_SDIVSHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S3C2443_PLLCON_SDIVMASK (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S3C2443_MPLLCON S3C2443_CLKREG(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S3C2443_EPLLCON S3C2443_CLKREG(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S3C2443_CLKSRC S3C2443_CLKREG(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S3C2443_HCLKCON S3C2443_CLKREG(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C2443_PCLKCON S3C2443_CLKREG(0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S3C2443_SCLKCON S3C2443_CLKREG(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C2443_PWRMODE S3C2443_CLKREG(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define S3C2443_SWRST S3C2443_CLKREG(0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S3C2443_SYSID S3C2443_CLKREG(0x5C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S3C2443_PWRCFG S3C2443_CLKREG(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S3C2443_RSTCON S3C2443_CLKREG(0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S3C2443_PHYCTRL S3C2443_CLKREG(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S3C2443_PHYPWR S3C2443_CLKREG(0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S3C2443_URSTCON S3C2443_CLKREG(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S3C2443_UCLKCON S3C2443_CLKREG(0x8C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S3C2443_PLLCON_OFF (1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S3C2443_CLKSRC_EPLLREF_MASK (3<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define S3C2443_CLKSRC_EXTCLK_DIV (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define S3C2443_CLKDIV0_HALF_HCLK (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define S3C2443_CLKDIV0_HALF_PCLK (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S3C2443_CLKDIV0_EXTDIV_SHIFT (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define S3C2443_CLKDIV0_PREDIV_MASK (3<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S3C2443_CLKDIV0_PREDIV_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define S3C2416_CLKDIV0_ARMDIV_MASK (7 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define S3C2443_CLKDIV0_ARMDIV_SHIFT (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define S3C2443_CLKDIV0_ARMDIV_1 (0<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define S3C2443_CLKDIV0_ARMDIV_2 (8<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define S3C2443_CLKDIV0_ARMDIV_3 (2<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define S3C2443_CLKDIV0_ARMDIV_4 (9<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define S3C2443_CLKDIV0_ARMDIV_6 (10<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define S3C2443_CLKDIV0_ARMDIV_8 (11<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define S3C2443_CLKDIV0_ARMDIV_12 (13<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define S3C2443_CLKDIV0_ARMDIV_16 (15<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* S3C2443_CLKDIV1 removed, only used in clock.c code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define S3C2443_CLKCON_NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define S3C2443_HCLKCON_DMA0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define S3C2443_HCLKCON_DMA1 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define S3C2443_HCLKCON_DMA2 (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define S3C2443_HCLKCON_DMA3 (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define S3C2443_HCLKCON_DMA4 (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define S3C2443_HCLKCON_DMA5 (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define S3C2443_HCLKCON_CAMIF (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define S3C2443_HCLKCON_LCDC (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define S3C2443_HCLKCON_USBH (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define S3C2443_HCLKCON_USBD (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define S3C2416_HCLKCON_HSMMC0 (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define S3C2443_HCLKCON_HSMMC (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define S3C2443_HCLKCON_CFC (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define S3C2443_HCLKCON_SSMC (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define S3C2443_HCLKCON_DRAMC (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define S3C2443_PCLKCON_UART0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define S3C2443_PCLKCON_UART1 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define S3C2443_PCLKCON_UART2 (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define S3C2443_PCLKCON_UART3 (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define S3C2443_PCLKCON_IIC (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define S3C2443_PCLKCON_SDI (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define S3C2443_PCLKCON_HSSPI (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define S3C2443_PCLKCON_ADC (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define S3C2443_PCLKCON_AC97 (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define S3C2443_PCLKCON_IIS (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define S3C2443_PCLKCON_PWMT (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define S3C2443_PCLKCON_WDT (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define S3C2443_PCLKCON_RTC (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define S3C2443_PCLKCON_GPIO (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define S3C2443_PCLKCON_SPI0 (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define S3C2443_PCLKCON_SPI1 (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define S3C2443_SCLKCON_DDRCLK (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define S3C2443_SCLKCON_SSMCCLK (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define S3C2443_SCLKCON_HSSPICLK (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define S3C2443_SCLKCON_CAMCLK (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define S3C2443_SCLKCON_DISPCLK (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define S3C2443_SCLKCON_I2SCLK (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define S3C2443_SCLKCON_UARTCLK (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define S3C2443_SCLKCON_USBHOST (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define S3C2443_PWRCFG_SLEEP (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define S3C2443_PWRCFG_USBPHY (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define S3C2443_URSTCON_FUNCRST (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define S3C2443_URSTCON_PHYRST (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define S3C2443_PHYCTRL_CLKSEL (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define S3C2443_PHYCTRL_EXTCLK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define S3C2443_PHYCTRL_PLLSEL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define S3C2443_PHYCTRL_DSPORT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define S3C2443_PHYPWR_COMMON_ON (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define S3C2443_PHYPWR_ANALOG_PD (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define S3C2443_PHYPWR_PLL_REFCLK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define S3C2443_PHYPWR_XO_ON (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define S3C2443_PHYPWR_PLL_PWRDN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define S3C2443_PHYPWR_FSUSPEND (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define S3C2443_UCLKCON_DETECT_VBUS (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define S3C2443_UCLKCON_FUNC_CLKEN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define S3C2443_UCLKCON_TCLKEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int mdiv, pdiv, sdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) uint64_t fvco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mdiv &= S3C2443_PLLCON_MDIVMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pdiv &= S3C2443_PLLCON_PDIVMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) sdiv &= S3C2443_PLLCON_SDIVMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) do_div(fvco, pdiv << sdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return (unsigned int)fvco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int mdiv, pdiv, sdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) uint64_t fvco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mdiv &= S3C2443_PLLCON_MDIVMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pdiv &= S3C2443_PLLCON_PDIVMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) sdiv &= S3C2443_PLLCON_SDIVMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) fvco = (uint64_t)baseclk * (mdiv + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) do_div(fvco, (pdiv + 2) << sdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return (unsigned int)fvco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static inline void s3c_hsudc_init_phy(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) writel(cfg, S3C2443_PWRCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) cfg = readl(S3C2443_URSTCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel(cfg, S3C2443_URSTCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) cfg = readl(S3C2443_URSTCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel(cfg, S3C2443_URSTCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) cfg = readl(S3C2443_PHYCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) writel(cfg, S3C2443_PHYCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) cfg = readl(S3C2443_PHYPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) S3C2443_PHYPWR_ANALOG_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cfg |= S3C2443_PHYPWR_COMMON_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) writel(cfg, S3C2443_PHYPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) cfg = readl(S3C2443_UCLKCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) S3C2443_UCLKCON_TCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writel(cfg, S3C2443_UCLKCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static inline void s3c_hsudc_uninit_phy(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) writel(cfg, S3C2443_PWRCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) writel(cfg, S3C2443_UCLKCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif /* __ASM_ARM_REGS_S3C2443_CLOCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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