Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *		      http://www.simtec.co.uk/products/SWLINUX/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef ___ASM_ARCH_REGS_IRQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define ___ASM_ARCH_REGS_IRQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "map-s3c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* interrupt controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define S3C2410_IRQREG(x)   ((x) + S3C24XX_VA_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define S3C2410_EINTREG(x)  ((x) + S3C24XX_VA_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S3C24XX_EINTREG(x)  ((x) + S3C24XX_VA_GPIO2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S3C2410_SRCPND	       S3C2410_IRQREG(0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S3C2410_INTMOD	       S3C2410_IRQREG(0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S3C2410_INTMSK	       S3C2410_IRQREG(0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S3C2410_PRIORITY       S3C2410_IRQREG(0x00C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S3C2410_INTPND	       S3C2410_IRQREG(0x010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define S3C2410_INTOFFSET      S3C2410_IRQREG(0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S3C2410_SUBSRCPND      S3C2410_IRQREG(0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S3C2410_INTSUBMSK      S3C2410_IRQREG(0x01C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S3C2416_PRIORITY_MODE1		S3C2410_IRQREG(0x030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define S3C2416_PRIORITY_UPDATE1	S3C2410_IRQREG(0x034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S3C2416_SRCPND2			S3C2410_IRQREG(0x040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C2416_INTMOD2			S3C2410_IRQREG(0x044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S3C2416_INTMSK2			S3C2410_IRQREG(0x048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C2416_INTPND2			S3C2410_IRQREG(0x050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define S3C2416_INTOFFSET2		S3C2410_IRQREG(0x054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S3C2416_PRIORITY_MODE2		S3C2410_IRQREG(0x070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S3C2416_PRIORITY_UPDATE2	S3C2410_IRQREG(0x074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* mask: 0=enable, 1=disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  * 1 bit EINT, 4=EINT4, 23=EINT23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  * EINT0,1,2,3 are not handled here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S3C2410_EINTMASK       S3C2410_EINTREG(0x0A4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S3C2410_EINTPEND       S3C2410_EINTREG(0X0A8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S3C2412_EINTMASK       S3C2410_EINTREG(0x0B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C2412_EINTPEND       S3C2410_EINTREG(0X0B8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S3C24XX_EINTMASK       S3C24XX_EINTREG(0x0A4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S3C24XX_EINTPEND       S3C24XX_EINTREG(0X0A8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif /* ___ASM_ARCH_REGS_IRQ_H */