Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2008 Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *      Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *      http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * S3C64XX - GPIO register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* Base addresses for each of the banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define S3C64XX_GPIOREG(reg)	(S3C64XX_VA_GPIO + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define S3C64XX_GPA_BASE	S3C64XX_GPIOREG(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define S3C64XX_GPB_BASE	S3C64XX_GPIOREG(0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define S3C64XX_GPC_BASE	S3C64XX_GPIOREG(0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define S3C64XX_GPD_BASE	S3C64XX_GPIOREG(0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define S3C64XX_GPE_BASE	S3C64XX_GPIOREG(0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define S3C64XX_GPF_BASE	S3C64XX_GPIOREG(0x00A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define S3C64XX_GPG_BASE	S3C64XX_GPIOREG(0x00C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define S3C64XX_GPH_BASE	S3C64XX_GPIOREG(0x00E0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define S3C64XX_GPI_BASE	S3C64XX_GPIOREG(0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define S3C64XX_GPJ_BASE	S3C64XX_GPIOREG(0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define S3C64XX_GPK_BASE	S3C64XX_GPIOREG(0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define S3C64XX_GPL_BASE	S3C64XX_GPIOREG(0x0810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define S3C64XX_GPM_BASE	S3C64XX_GPIOREG(0x0820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define S3C64XX_GPN_BASE	S3C64XX_GPIOREG(0x0830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define S3C64XX_GPO_BASE	S3C64XX_GPIOREG(0x0140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define S3C64XX_GPP_BASE	S3C64XX_GPIOREG(0x0160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define S3C64XX_GPQ_BASE	S3C64XX_GPIOREG(0x0180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* SPCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define S3C64XX_SPCON		S3C64XX_GPIOREG(0x1A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define S3C64XX_SPCON_DRVCON_CAM_MASK		(0x3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define S3C64XX_SPCON_DRVCON_CAM_SHIFT		(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define S3C64XX_SPCON_DRVCON_CAM_2mA		(0x0 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define S3C64XX_SPCON_DRVCON_CAM_4mA		(0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define S3C64XX_SPCON_DRVCON_CAM_7mA		(0x2 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define S3C64XX_SPCON_DRVCON_CAM_9mA		(0x3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define S3C64XX_SPCON_DRVCON_HSSPI_MASK		(0x3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT	(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define S3C64XX_SPCON_DRVCON_HSSPI_2mA		(0x0 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define S3C64XX_SPCON_DRVCON_HSSPI_4mA		(0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define S3C64XX_SPCON_DRVCON_HSSPI_7mA		(0x2 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define S3C64XX_SPCON_DRVCON_HSSPI_9mA		(0x3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define S3C64XX_SPCON_DRVCON_HSMMC_MASK		(0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT	(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define S3C64XX_SPCON_DRVCON_HSMMC_2mA		(0x0 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define S3C64XX_SPCON_DRVCON_HSMMC_4mA		(0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define S3C64XX_SPCON_DRVCON_HSMMC_7mA		(0x2 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define S3C64XX_SPCON_DRVCON_HSMMC_9mA		(0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define S3C64XX_SPCON_DRVCON_LCD_MASK		(0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define S3C64XX_SPCON_DRVCON_LCD_SHIFT		(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define S3C64XX_SPCON_DRVCON_LCD_2mA		(0x0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define S3C64XX_SPCON_DRVCON_LCD_4mA		(0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define S3C64XX_SPCON_DRVCON_LCD_7mA		(0x2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define S3C64XX_SPCON_DRVCON_LCD_9mA		(0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define S3C64XX_SPCON_DRVCON_MODEM_MASK		(0x3 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define S3C64XX_SPCON_DRVCON_MODEM_SHIFT	(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define S3C64XX_SPCON_DRVCON_MODEM_2mA		(0x0 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define S3C64XX_SPCON_DRVCON_MODEM_4mA		(0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define S3C64XX_SPCON_DRVCON_MODEM_7mA		(0x2 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define S3C64XX_SPCON_DRVCON_MODEM_9mA		(0x3 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define S3C64XX_SPCON_nRSTOUT_OEN		(1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define S3C64XX_SPCON_DRVCON_SPICLK1_MASK	(0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT	(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define S3C64XX_SPCON_DRVCON_SPICLK1_2mA	(0x0 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define S3C64XX_SPCON_DRVCON_SPICLK1_4mA	(0x1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define S3C64XX_SPCON_DRVCON_SPICLK1_7mA	(0x2 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define S3C64XX_SPCON_DRVCON_SPICLK1_9mA	(0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define S3C64XX_SPCON_MEM1_DQS_PUD_MASK		(0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT	(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED	(0x0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN		(0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define S3C64XX_SPCON_MEM1_DQS_PUD_UP		(0x2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define S3C64XX_SPCON_MEM1_D_PUD1_MASK		(0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT		(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED	(0x0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define S3C64XX_SPCON_MEM1_D_PUD1_DOWN		(0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define S3C64XX_SPCON_MEM1_D_PUD1_UP		(0x2 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define S3C64XX_SPCON_MEM1_D_PUD0_MASK		(0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT		(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED	(0x0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define S3C64XX_SPCON_MEM1_D_PUD0_DOWN		(0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define S3C64XX_SPCON_MEM1_D_PUD0_UP		(0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define S3C64XX_SPCON_MEM0_D_PUD_MASK		(0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define S3C64XX_SPCON_MEM0_D_PUD_SHIFT		(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define S3C64XX_SPCON_MEM0_D_PUD_DISABLED	(0x0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define S3C64XX_SPCON_MEM0_D_PUD_DOWN		(0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define S3C64XX_SPCON_MEM0_D_PUD_UP		(0x2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define S3C64XX_SPCON_USBH_DMPD			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define S3C64XX_SPCON_USBH_DPPD			(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define S3C64XX_SPCON_USBH_PUSW2		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define S3C64XX_SPCON_USBH_PUSW1		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define S3C64XX_SPCON_USBH_SUSPND		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define S3C64XX_SPCON_LCD_SEL_MASK		(0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define S3C64XX_SPCON_LCD_SEL_SHIFT		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define S3C64XX_SPCON_LCD_SEL_HOST		(0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define S3C64XX_SPCON_LCD_SEL_RGB		(0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define S3C64XX_SPCON_LCD_SEL_606_656		(0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* External interrupt registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define S3C64XX_EINT12CON	S3C64XX_GPIOREG(0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define S3C64XX_EINT34CON	S3C64XX_GPIOREG(0x204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define S3C64XX_EINT56CON	S3C64XX_GPIOREG(0x208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define S3C64XX_EINT78CON	S3C64XX_GPIOREG(0x20C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define S3C64XX_EINT9CON	S3C64XX_GPIOREG(0x210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define S3C64XX_EINT12FLTCON	S3C64XX_GPIOREG(0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define S3C64XX_EINT34FLTCON	S3C64XX_GPIOREG(0x224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define S3C64XX_EINT56FLTCON	S3C64XX_GPIOREG(0x228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define S3C64XX_EINT78FLTCON	S3C64XX_GPIOREG(0x22C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define S3C64XX_EINT9FLTCON	S3C64XX_GPIOREG(0x230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define S3C64XX_EINT12MASK	S3C64XX_GPIOREG(0x240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define S3C64XX_EINT34MASK	S3C64XX_GPIOREG(0x244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define S3C64XX_EINT56MASK	S3C64XX_GPIOREG(0x248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define S3C64XX_EINT78MASK	S3C64XX_GPIOREG(0x24C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define S3C64XX_EINT9MASK	S3C64XX_GPIOREG(0x250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define S3C64XX_EINT12PEND	S3C64XX_GPIOREG(0x260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define S3C64XX_EINT34PEND	S3C64XX_GPIOREG(0x264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define S3C64XX_EINT56PEND	S3C64XX_GPIOREG(0x268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define S3C64XX_EINT78PEND	S3C64XX_GPIOREG(0x26C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define S3C64XX_EINT9PEND	S3C64XX_GPIOREG(0x270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define S3C64XX_PRIORITY	S3C64XX_GPIOREG(0x280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define S3C64XX_PRIORITY_ARB(x)	(1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define S3C64XX_SERVICE		S3C64XX_GPIOREG(0x284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define S3C64XX_SERVICEPEND	S3C64XX_GPIOREG(0x288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define S3C64XX_EINT0CON0	S3C64XX_GPIOREG(0x900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define S3C64XX_EINT0CON1	S3C64XX_GPIOREG(0x904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define S3C64XX_EINT0FLTCON0	S3C64XX_GPIOREG(0x910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define S3C64XX_EINT0FLTCON1	S3C64XX_GPIOREG(0x914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define S3C64XX_EINT0FLTCON2	S3C64XX_GPIOREG(0x918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define S3C64XX_EINT0FLTCON3	S3C64XX_GPIOREG(0x91C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define S3C64XX_EINT0MASK	S3C64XX_GPIOREG(0x920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define S3C64XX_EINT0PEND	S3C64XX_GPIOREG(0x924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* GPIO sleep configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define S3C64XX_SPCONSLP	S3C64XX_GPIOREG(0x880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define S3C64XX_SPCONSLP_TDO_PULLDOWN	(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define S3C64XX_SPCONSLP_CKE1INIT	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define S3C64XX_SPCONSLP_RSTOUT_MASK	(0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define S3C64XX_SPCONSLP_RSTOUT_OUT0	(0x0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define S3C64XX_SPCONSLP_RSTOUT_OUT1	(0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define S3C64XX_SPCONSLP_RSTOUT_HIZ	(0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define S3C64XX_SPCONSLP_KPCOL_MASK	(0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define S3C64XX_SPCONSLP_KPCOL_OUT0	(0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define S3C64XX_SPCONSLP_KPCOL_OUT1	(0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define S3C64XX_SPCONSLP_KPCOL_INP	(0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define S3C64XX_SLPEN		S3C64XX_GPIOREG(0x930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define S3C64XX_SLPEN_USE_xSLP		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define S3C64XX_SLPEN_CFG_BYSLPEN	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)