^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * http://www.simtec.co.uk/products/SWLINUX/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * S3C2410 GPIO register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __ASM_ARCH_REGS_GPIO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __ASM_ARCH_REGS_GPIO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "map-s3c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* general configuration options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S3C2410_GPIO_OUTPUT (0xFFFFFFF1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* register address for the GPIO registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * S3C24XX_GPIOREG2 is for the second set of registers in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * GPIO which move between s3c2410 and s3c2412 type systems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* configure GPIO ports A..G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* port A - S3C2410: 22bits, zero in bit X makes pin X output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 1 makes port special function, this is default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S3C2410_GPACON S3C2410_GPIOREG(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S3C2410_GPA0_ADDR0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S3C2410_GPA1_ADDR16 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S3C2410_GPA2_ADDR17 (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S3C2410_GPA3_ADDR18 (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C2410_GPA4_ADDR19 (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S3C2410_GPA5_ADDR20 (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S3C2410_GPA6_ADDR21 (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S3C2410_GPA7_ADDR22 (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S3C2410_GPA8_ADDR23 (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define S3C2410_GPA9_ADDR24 (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define S3C2410_GPA10_ADDR25 (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define S3C2410_GPA11_ADDR26 (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define S3C2410_GPA12_nGCS1 (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define S3C2410_GPA13_nGCS2 (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define S3C2410_GPA14_nGCS3 (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define S3C2410_GPA15_nGCS4 (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define S3C2410_GPA16_nGCS5 (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define S3C2410_GPA17_CLE (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S3C2410_GPA18_ALE (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define S3C2410_GPA19_nFWE (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define S3C2410_GPA20_nFRE (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S3C2410_GPA21_nRSTOUT (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define S3C2410_GPA22_nFCE (1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* 0x08 and 0x0c are reserved on S3C2410 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* S3C2410:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * 00 = input, 01 = output, 10=special function, 11=reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * bit 0,1 = pin 0, 2,3= pin 1...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * CPBUP = pull up resistor control, 1=disabled, 0=enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define S3C2410_GPBCON S3C2410_GPIOREG(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define S3C2410_GPBUP S3C2410_GPIOREG(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define S3C2410_GPB0_TOUT0 (0x02 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define S3C2410_GPB1_TOUT1 (0x02 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define S3C2410_GPB2_TOUT2 (0x02 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define S3C2410_GPB3_TOUT3 (0x02 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define S3C2410_GPB4_TCLK0 (0x02 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define S3C2410_GPB4_MASK (0x03 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define S3C2410_GPB5_nXBACK (0x02 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define S3C2443_GPB5_XBACK (0x03 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define S3C2410_GPB6_nXBREQ (0x02 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define S3C2443_GPB6_XBREQ (0x03 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define S3C2410_GPB7_nXDACK1 (0x02 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define S3C2443_GPB7_XDACK1 (0x03 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define S3C2410_GPB9_nXDACK0 (0x02 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define S3C2443_GPB9_XDACK0 (0x03 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define S3C2410_GPB10_nXDRE0 (0x02 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define S3C2443_GPB10_XDREQ0 (0x03 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define S3C2410_GPB_PUPDIS(x) (1<<(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Port C consits of 16 GPIO/Special function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * almost identical setup to port b, but the special functions are mostly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * to do with the video system's sync/etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define S3C2410_GPCCON S3C2410_GPIOREG(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define S3C2410_GPC0_LEND (0x02 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define S3C2410_GPC1_VCLK (0x02 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define S3C2410_GPC2_VLINE (0x02 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define S3C2410_GPC3_VFRAME (0x02 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define S3C2410_GPC4_VM (0x02 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define S3C2410_GPC5_LCDVF0 (0x02 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define S3C2410_GPC6_LCDVF1 (0x02 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define S3C2410_GPC7_LCDVF2 (0x02 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define S3C2410_GPC8_VD0 (0x02 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define S3C2410_GPC9_VD1 (0x02 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define S3C2410_GPC10_VD2 (0x02 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define S3C2410_GPC11_VD3 (0x02 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define S3C2410_GPC12_VD4 (0x02 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define S3C2410_GPC13_VD5 (0x02 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define S3C2410_GPC14_VD6 (0x02 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define S3C2410_GPC15_VD7 (0x02 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define S3C2410_GPC_PUPDIS(x) (1<<(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * S3C2410: Port D consists of 16 GPIO/Special function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * almost identical setup to port b, but the special functions are mostly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * to do with the video system's data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * almost identical setup to port c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define S3C2410_GPDCON S3C2410_GPIOREG(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define S3C2410_GPD0_VD8 (0x02 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define S3C2442_GPD0_nSPICS1 (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define S3C2410_GPD1_VD9 (0x02 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define S3C2442_GPD1_SPICLK1 (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define S3C2410_GPD2_VD10 (0x02 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define S3C2410_GPD3_VD11 (0x02 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define S3C2410_GPD4_VD12 (0x02 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define S3C2410_GPD5_VD13 (0x02 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define S3C2410_GPD6_VD14 (0x02 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define S3C2410_GPD7_VD15 (0x02 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define S3C2410_GPD8_VD16 (0x02 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define S3C2440_GPD8_SPIMISO1 (0x03 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define S3C2410_GPD9_VD17 (0x02 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define S3C2440_GPD9_SPIMOSI1 (0x03 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define S3C2410_GPD10_VD18 (0x02 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define S3C2440_GPD10_SPICLK1 (0x03 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define S3C2410_GPD11_VD19 (0x02 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define S3C2410_GPD12_VD20 (0x02 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define S3C2410_GPD13_VD21 (0x02 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define S3C2410_GPD14_VD22 (0x02 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define S3C2410_GPD14_nSS1 (0x03 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define S3C2410_GPD15_VD23 (0x02 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define S3C2410_GPD15_nSS0 (0x03 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define S3C2410_GPD_PUPDIS(x) (1<<(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* S3C2410:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Port E consists of 16 GPIO/Special function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * again, the same as port B, but dealing with I2S, SDI, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * more miscellaneous functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * GPIO / interrupt inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define S3C2410_GPECON S3C2410_GPIOREG(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define S3C2410_GPE0_I2SLRCK (0x02 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define S3C2443_GPE0_AC_nRESET (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define S3C2410_GPE0_MASK (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define S3C2410_GPE1_I2SSCLK (0x02 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define S3C2443_GPE1_AC_SYNC (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define S3C2410_GPE1_MASK (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define S3C2410_GPE2_CDCLK (0x02 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define S3C2410_GPE3_I2SSDI (0x02 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define S3C2443_GPE3_AC_SDI (0x03 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define S3C2410_GPE3_nSS0 (0x03 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define S3C2410_GPE3_MASK (0x03 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define S3C2410_GPE4_I2SSDO (0x02 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define S3C2443_GPE4_AC_SDO (0x03 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define S3C2410_GPE4_I2SSDI (0x03 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define S3C2410_GPE4_MASK (0x03 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define S3C2410_GPE5_SDCLK (0x02 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define S3C2443_GPE5_SD1_CLK (0x02 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define S3C2443_GPE5_AC_BITCLK (0x03 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define S3C2410_GPE6_SDCMD (0x02 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define S3C2443_GPE6_SD1_CMD (0x02 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define S3C2443_GPE6_AC_SDI (0x03 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define S3C2410_GPE7_SDDAT0 (0x02 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define S3C2443_GPE7_AC_SDO (0x03 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define S3C2410_GPE8_SDDAT1 (0x02 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define S3C2443_GPE8_AC_SYNC (0x03 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define S3C2410_GPE9_SDDAT2 (0x02 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define S3C2443_GPE9_AC_nRESET (0x03 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define S3C2410_GPE10_SDDAT3 (0x02 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define S3C2410_GPE13_SPICLK0 (0x02 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define S3C2410_GPE14_IICSCL (0x02 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define S3C2410_GPE14_MASK (0x03 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define S3C2410_GPE15_IICSDA (0x02 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define S3C2410_GPE15_MASK (0x03 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define S3C2440_GPE0_ACSYNC (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define S3C2440_GPE1_ACBITCLK (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define S3C2440_GPE2_ACRESET (0x03 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define S3C2440_GPE3_ACIN (0x03 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define S3C2440_GPE4_ACOUT (0x03 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define S3C2410_GPE_PUPDIS(x) (1<<(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* S3C2410:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Port F consists of 8 GPIO/Special function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * GPIO / interrupt inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * GPFCON has 2 bits for each of the input pins on port F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * pull up works like all other ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * GPIO/serial/misc pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define S3C2410_GPFCON S3C2410_GPIOREG(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define S3C2410_GPF0_EINT0 (0x02 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define S3C2410_GPF1_EINT1 (0x02 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define S3C2410_GPF2_EINT2 (0x02 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define S3C2410_GPF3_EINT3 (0x02 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define S3C2410_GPF4_EINT4 (0x02 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define S3C2410_GPF5_EINT5 (0x02 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define S3C2410_GPF6_EINT6 (0x02 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define S3C2410_GPF7_EINT7 (0x02 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define S3C2410_GPF_PUPDIS(x) (1<<(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* S3C2410:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Port G consists of 8 GPIO/IRQ/Special function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * GPGCON has 2 bits for each of the input pins on port G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * pull up works like all other ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define S3C2410_GPGCON S3C2410_GPIOREG(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define S3C2410_GPG0_EINT8 (0x02 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define S3C2410_GPG1_EINT9 (0x02 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define S3C2410_GPG2_EINT10 (0x02 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define S3C2410_GPG2_nSS0 (0x03 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define S3C2410_GPG3_EINT11 (0x02 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define S3C2410_GPG3_nSS1 (0x03 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define S3C2410_GPG4_EINT12 (0x02 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define S3C2410_GPG4_LCDPWREN (0x03 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define S3C2410_GPG5_EINT13 (0x02 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define S3C2410_GPG6_EINT14 (0x02 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define S3C2410_GPG7_EINT15 (0x02 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define S3C2410_GPG7_SPICLK1 (0x03 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define S3C2410_GPG8_EINT16 (0x02 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define S3C2410_GPG9_EINT17 (0x02 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define S3C2410_GPG10_EINT18 (0x02 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define S3C2410_GPG11_EINT19 (0x02 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define S3C2410_GPG11_TCLK1 (0x03 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define S3C2410_GPG12_EINT20 (0x02 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define S3C2410_GPG12_XMON (0x03 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define S3C2442_GPG12_nSPICS0 (0x03 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define S3C2443_GPG12_nINPACK (0x03 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define S3C2410_GPG13_EINT21 (0x02 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define S3C2410_GPG13_nXPON (0x03 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define S3C2443_GPG13_CF_nREG (0x03 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define S3C2410_GPG14_EINT22 (0x02 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define S3C2410_GPG14_YMON (0x03 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define S3C2443_GPG14_CF_RESET (0x03 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define S3C2410_GPG15_EINT23 (0x02 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define S3C2410_GPG15_nYPON (0x03 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define S3C2443_GPG15_CF_PWR (0x03 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define S3C2410_GPG_PUPDIS(x) (1<<(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Port H consists of11 GPIO/serial/Misc pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * GPHCON has 2 bits for each of the input pins on port H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * pull up works like all other ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define S3C2410_GPHCON S3C2410_GPIOREG(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define S3C2410_GPH0_nCTS0 (0x02 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define S3C2416_GPH0_TXD0 (0x02 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define S3C2410_GPH1_nRTS0 (0x02 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define S3C2416_GPH1_RXD0 (0x02 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define S3C2410_GPH2_TXD0 (0x02 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define S3C2416_GPH2_TXD1 (0x02 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define S3C2410_GPH3_RXD0 (0x02 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define S3C2416_GPH3_RXD1 (0x02 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define S3C2410_GPH4_TXD1 (0x02 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define S3C2416_GPH4_TXD2 (0x02 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define S3C2410_GPH5_RXD1 (0x02 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define S3C2416_GPH5_RXD2 (0x02 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define S3C2410_GPH6_TXD2 (0x02 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define S3C2416_GPH6_TXD3 (0x02 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define S3C2410_GPH6_nRTS1 (0x03 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define S3C2416_GPH6_nRTS2 (0x03 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define S3C2410_GPH7_RXD2 (0x02 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define S3C2416_GPH7_RXD3 (0x02 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define S3C2410_GPH7_nCTS1 (0x03 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define S3C2416_GPH7_nCTS2 (0x03 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define S3C2410_GPH8_UCLK (0x02 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define S3C2416_GPH8_nCTS0 (0x02 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define S3C2442_GPH9_nSPICS0 (0x03 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define S3C2416_GPH9_nRTS0 (0x02 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define S3C2416_GPH10_nCTS1 (0x02 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define S3C2416_GPH11_nRTS1 (0x02 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define S3C2416_GPH12_EXTUARTCLK (0x02 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define S3C2416_GPH13_CLKOUT0 (0x02 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define S3C2416_GPH14_CLKOUT1 (0x02 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* The S3C2412 and S3C2413 move the GPJ register set to after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * GPH, which means all registers after 0x80 are now offset by 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * for the 2412/2413 from the 2410/2440/2442
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * Port J consists of 13 GPIO/Camera pins. GPJCON has 2 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * for each of the pins on port J.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * 00 - input, 01 output, 10 - camera
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Pull up works like all other ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define S3C2413_GPJCON S3C2410_GPIOREG(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define S3C2413_GPJDAT S3C2410_GPIOREG(0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define S3C2413_GPJUP S3C2410_GPIOREG(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* S3C2443 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define S3C2440_GPJCON S3C2410_GPIOREG(0xD0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define S3C2440_GPJUP S3C2410_GPIOREG(0xD8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define S3C2443_GPKCON S3C2410_GPIOREG(0xE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define S3C2443_GPKUP S3C2410_GPIOREG(0xE8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define S3C2443_GPLCON S3C2410_GPIOREG(0xF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define S3C2443_GPLUP S3C2410_GPIOREG(0xF8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define S3C2443_GPMCON S3C2410_GPIOREG(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define S3C2443_GPMDAT S3C2410_GPIOREG(0x104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define S3C2443_GPMUP S3C2410_GPIOREG(0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* miscellaneous control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* see clock.h for dclk definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* pullup control on databus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define S3C2410_MISCCR_SPUCR_HEN (0<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define S3C2410_MISCCR_SPUCR_HDIS (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define S3C2410_MISCCR_SPUCR_LEN (0<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define S3C2410_MISCCR_SPUCR_LDIS (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define S3C2410_MISCCR_USBDEV (0<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define S3C2410_MISCCR_USBHOST (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define S3C2410_MISCCR_CLK0_MPLL (0<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define S3C2410_MISCCR_CLK0_UPLL (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define S3C2410_MISCCR_CLK0_FCLK (2<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define S3C2410_MISCCR_CLK0_HCLK (3<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define S3C2410_MISCCR_CLK0_PCLK (4<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define S3C2410_MISCCR_CLK0_MASK (7<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define S3C2412_MISCCR_CLK0_RTC (2<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define S3C2410_MISCCR_CLK1_MPLL (0<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define S3C2410_MISCCR_CLK1_UPLL (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define S3C2410_MISCCR_CLK1_FCLK (2<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define S3C2410_MISCCR_CLK1_HCLK (3<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define S3C2410_MISCCR_CLK1_PCLK (4<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define S3C2410_MISCCR_CLK1_MASK (7<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define S3C2412_MISCCR_CLK1_CLKsrc (0<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define S3C2410_MISCCR_USBSUSPND0 (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define S3C2416_MISCCR_SEL_SUSPND (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define S3C2410_MISCCR_USBSUSPND1 (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define S3C2410_MISCCR_nRSTCON (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define S3C2410_MISCCR_SDSLEEP (7<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define S3C2416_MISCCR_FLT_I2C (1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define S3C2416_MISCCR_HSSPI_EN2 (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* external interrupt control... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Samsung datasheet p9-25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* interrupt filtering control for EINT16..EINT23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* values for interrupt filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define S3C2410_EINTFLT_PCLK (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define S3C2410_EINTFLT_EXTCLK (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* removed EINTxxxx defs from here, not meant for this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* GSTATUS have miscellaneous information in them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * These move between s3c2410 and s3c2412 style systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define S3C2410_GSTATUS0_nWAIT (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define S3C2410_GSTATUS0_NCON (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define S3C2410_GSTATUS0_RnB (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define S3C2410_GSTATUS0_nBATTFLT (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define S3C2410_GSTATUS1_IDMASK (0xffff0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define S3C2410_GSTATUS1_2410 (0x32410000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define S3C2410_GSTATUS1_2412 (0x32412001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define S3C2410_GSTATUS1_2416 (0x32416003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define S3C2410_GSTATUS1_2440 (0x32440000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define S3C2410_GSTATUS1_2442 (0x32440aaa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* some 2416 CPUs report this value also */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define S3C2410_GSTATUS1_2450 (0x32450003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define S3C2410_GSTATUS2_WTRESET (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define S3C2410_GSTATUS2_OFFRESET (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define S3C2410_GSTATUS2_PONRESET (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* 2412/2413 sleep configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* definitions for each pin bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define S3C2412_GPIO_SLPCON_LOW ( 0x00 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define S3C2412_GPIO_SLPCON_IN ( 0x02 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define S3C2412_GPIO_SLPCON_PULL ( 0x03 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define S3C2412_SLPCON_ALL_LOW (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define S3C2412_SLPCON_ALL_PULL (0x33333333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #endif /* __ASM_ARCH_REGS_GPIO_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags