Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2008 Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *	http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * S3C64XX clock register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __PLAT_REGS_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __PLAT_REGS_CLOCK_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * FIXME: Remove remaining definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S3C_CLKREG(x)		(S3C_VA_SYS + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S3C_PCLK_GATE		S3C_CLKREG(0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S3C6410_CLK_SRC2	S3C_CLKREG(0x10C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S3C_MEM_SYS_CFG		S3C_CLKREG(0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* PCLK GATE Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S3C_CLKCON_PCLK_UART3		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S3C_CLKCON_PCLK_UART2		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S3C_CLKCON_PCLK_UART1		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S3C_CLKCON_PCLK_UART0		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* MEM_SYS_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MEM_SYS_CFG_INDEP_CF		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MEM_SYS_CFG_EBI_FIX_PRI_CFCON	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif /* _PLAT_REGS_CLOCK_H */