^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * S3C2410 clock register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __ASM_ARM_REGS_CLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ASM_ARM_REGS_CLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S3C2410_LOCKTIME S3C2410_CLKREG(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S3C2410_MPLLCON S3C2410_CLKREG(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S3C2410_UPLLCON S3C2410_CLKREG(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S3C2410_CLKCON S3C2410_CLKREG(0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S3C2410_CLKSLOW S3C2410_CLKREG(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S3C2410_CLKCON_IDLE (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S3C2410_CLKCON_POWER (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S3C2410_CLKCON_NAND (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S3C2410_CLKCON_LCDC (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define S3C2410_CLKCON_USBH (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S3C2410_CLKCON_USBD (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C2410_CLKCON_PWMT (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S3C2410_CLKCON_SDI (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C2410_CLKCON_UART0 (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define S3C2410_CLKCON_UART1 (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S3C2410_CLKCON_UART2 (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S3C2410_CLKCON_GPIO (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S3C2410_CLKCON_RTC (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S3C2410_CLKCON_ADC (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S3C2410_CLKCON_IIC (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S3C2410_CLKCON_IIS (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S3C2410_CLKCON_SPI (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S3C2410_CLKDIVN_PDIVN (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S3C2410_CLKDIVN_HDIVN (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C2410_CLKSLOW_UCLK_OFF (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S3C2410_CLKSLOW_MPLL_OFF (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S3C2410_CLKSLOW_SLOW (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S3C2410_CLKSLOW_SLOWVAL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* extra registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define S3C2440_CAMDIVN S3C2410_CLKREG(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define S3C2440_CLKCON_CAMERA (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define S3C2440_CLKCON_AC97 (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S3C2440_CLKDIVN_PDIVN (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define S3C2440_CLKDIVN_HDIVN_1 (0<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S3C2440_CLKDIVN_HDIVN_2 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define S3C2440_CLKDIVN_UCLK (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define S3C2440_CAMDIVN_DVSEN (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #if defined(CONFIG_CPU_S3C2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define S3C2412_OSCSET S3C2410_CLKREG(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define S3C2412_CLKSRC S3C2410_CLKREG(0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define S3C2412_PLLCON_OFF (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define S3C2412_CLKDIVN_PDIVN (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define S3C2412_CLKDIVN_HDIVN_MASK (3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define S3C2412_CLKDIVN_ARMDIVN (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define S3C2412_CLKDIVN_DVSEN (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define S3C2412_CLKDIVN_HALFHCLK (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define S3C2412_CLKDIVN_USB48DIV (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define S3C2412_CLKDIVN_UARTDIV_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define S3C2412_CLKDIVN_I2SDIV_SHIFT (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define S3C2412_CLKDIVN_CAMDIV_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define S3C2412_CLKCON_WDT (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define S3C2412_CLKCON_SPI (1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define S3C2412_CLKCON_IIS (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define S3C2412_CLKCON_IIC (1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define S3C2412_CLKCON_ADC (1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define S3C2412_CLKCON_RTC (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define S3C2412_CLKCON_GPIO (1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define S3C2412_CLKCON_UART2 (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define S3C2412_CLKCON_UART1 (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define S3C2412_CLKCON_UART0 (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define S3C2412_CLKCON_SDI (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define S3C2412_CLKCON_PWMT (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define S3C2412_CLKCON_USBD (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define S3C2412_CLKCON_CAMCLK (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define S3C2412_CLKCON_UARTCLK (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* missing 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define S3C2412_CLKCON_USB_HOST48 (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define S3C2412_CLKCON_USB_DEV48 (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define S3C2412_CLKCON_HCLKdiv2 (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define S3C2412_CLKCON_HCLKx2 (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define S3C2412_CLKCON_SDRAM (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* missing 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define S3C2412_CLKCON_DMA3 (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define S3C2412_CLKCON_DMA2 (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define S3C2412_CLKCON_DMA1 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define S3C2412_CLKCON_DMA0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* clock sourec controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define S3C2412_CLKSRC_USBCLK_HCLK (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #endif /* CONFIG_CPU_S3C2412 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define S3C2416_CLKDIV2 S3C2410_CLKREG(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #endif /* __ASM_ARM_REGS_CLOCK */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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