Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2004 Shannon Holland <holland@loser.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * S3C2410 ADC registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __ASM_ARCH_REGS_ADC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define S3C2410_ADCREG(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define S3C2410_ADCCON	   S3C2410_ADCREG(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define S3C2410_ADCTSC	   S3C2410_ADCREG(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define S3C2410_ADCDLY	   S3C2410_ADCREG(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define S3C2410_ADCDAT0	   S3C2410_ADCREG(0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S3C2410_ADCDAT1	   S3C2410_ADCREG(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S3C64XX_ADCUPDN		S3C2410_ADCREG(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S3C2443_ADCMUX		S3C2410_ADCREG(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S3C64XX_ADCCLRINT	S3C2410_ADCREG(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S5P_ADCMUX		S3C2410_ADCREG(0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S3C64XX_ADCCLRINTPNDNUP	S3C2410_ADCREG(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* ADCCON Register Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S3C64XX_ADCCON_RESSEL		(1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S3C2410_ADCCON_ECFLG		(1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S3C2410_ADCCON_PRSCEN		(1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define S3C2410_ADCCON_PRSCVL(x)	(((x)&0xFF)<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S3C2410_ADCCON_PRSCVLMASK	(0xFF<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C2410_ADCCON_SELMUX(x)	(((x)&0x7)<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S3C2410_ADCCON_MUXMASK		(0x7<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C2416_ADCCON_RESSEL		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define S3C2410_ADCCON_STDBM		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S3C2410_ADCCON_READ_START	(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S3C2410_ADCCON_ENABLE_START	(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S3C2410_ADCCON_STARTMASK	(0x3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* ADCTSC Register Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S3C2443_ADCTSC_UD_SEN		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S3C2410_ADCTSC_YM_SEN		(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S3C2410_ADCTSC_YP_SEN		(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S3C2410_ADCTSC_XM_SEN		(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S3C2410_ADCTSC_XP_SEN		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C2410_ADCTSC_PULL_UP_DISABLE	(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S3C2410_ADCTSC_AUTO_PST		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S3C2410_ADCTSC_XY_PST(x)	(((x)&0x3)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* ADCDAT0 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define S3C2410_ADCDAT0_UPDOWN		(1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define S3C2410_ADCDAT0_AUTO_PST	(1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define S3C2410_ADCDAT0_XY_PST		(0x3<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define S3C2410_ADCDAT0_XPDATA_MASK	(0x03FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* ADCDAT1 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define S3C2410_ADCDAT1_UPDOWN		(1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define S3C2410_ADCDAT1_AUTO_PST	(1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define S3C2410_ADCDAT1_XY_PST		(0x3<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S3C2410_ADCDAT1_YPDATA_MASK	(0x03FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif /* __ASM_ARCH_REGS_ADC_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)